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RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2001.903262openalex-snapshot
Dynamic prediction of critical path instructions
inferredcites →https://doi.org/10.1109/hpca.2006.1598116openalex-snapshot
Construction and Use of Linear Regression Models for Processor Performance Analysis
inferredcites →https://doi.org/10.1109/hpca.2007.346211openalex-snapshot
Illustrative Design Space Studies with Microarchitectural Regression Models
inferredcites →https://doi.org/10.1109/hpca.2009.4798280openalex-snapshot
Criticality-based optimizations for efficient load processing
inferredcites →https://doi.org/10.1109/hpca.2010.5416635openalex-snapshot
Graphite: A distributed parallel simulator for multicores
inferredcites →https://doi.org/10.1109/hpca.2011.5749747openalex-snapshot
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
inferredcites →https://doi.org/10.1109/iiswc.2011.6114195openalex-snapshot
Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads
inferredcites →https://doi.org/10.1109/isca.2001.937434openalex-snapshot
Focusing processor policies via critical-path prediction
inferredcites →https://doi.org/10.1109/isca.2002.1003557openalex-snapshot
The optimum pipeline depth for a microprocessor
inferredcites →https://doi.org/10.1109/isca.2002.1003561openalex-snapshot
Slack: maximizing performance under technological constraints
inferredcites →https://doi.org/10.1109/isca.2004.1310786openalex-snapshot
A first-order superscalar processor model
inferredcites →https://doi.org/10.1109/isca.2008.39openalex-snapshot
Fetch-Criticality Reduction through Control Independence
inferredcites →https://doi.org/10.1109/ispass.2008.4510739openalex-snapshot
Full-System Critical Path Analysis
inferredcites →https://doi.org/10.1109/micro.1997.645821openalex-snapshot
ProfileMe: hardware support for instruction-level profiling on out-of-order processors
inferredcites →https://doi.org/10.1109/micro.2007.36openalex-snapshot
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
inferredcites →https://doi.org/10.1109/micro.2008.4771797openalex-snapshot
CPR: Composable performance regression for scalable multiprocessor models
inferredcites →https://doi.org/10.1109/pact.2002.1106008openalex-snapshot
Quantifying instruction criticality
inferredcites →https://doi.org/10.1145/1022969.1022971openalex-snapshot
Interaction cost and shotgun profiling
inferredcites →https://doi.org/10.1145/1028176.1006729openalex-snapshot
A First-Order Superscalar Processor Model
inferredcites →https://doi.org/10.1145/1168857.1168880openalex-snapshot
A performance counter architecture for computing accurate CPI components
inferredcites →https://doi.org/10.1145/1168857.1168881openalex-snapshot
Accurate and efficient regression modeling for microarchitectural performance and power prediction
inferredcites →https://doi.org/10.1145/1346281.1346288openalex-snapshot
Efficiency trends and limits from comprehensive microarchitectural adaptivity
inferredcites →https://doi.org/10.1145/1394608.1382170openalex-snapshot
Fetch-Criticality Reduction through Control Independence
inferredcites →https://doi.org/10.1145/1534909.1534910openalex-snapshot
A mechanistic performance model for superscalar out-of-order processors
inferredcites →https://doi.org/10.1145/369028.369059openalex-snapshot
Performance analysis using the MIPS R10000 performance counters
inferredcites →https://doi.org/10.1145/379240.379253openalex-snapshot
Focusing processor policies via critical-path prediction
inferredcites →https://doi.org/10.1145/545214.545217openalex-snapshot
The optimum pipeline depth for a microprocessor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1147/rd.413.0215openalex-snapshot
Understanding some simple processor-performance limits
inferredcites →https://doi.org/10.5555/1331699.1331723openalex-snapshot
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
inferredcites →https://doi.org/10.5555/266800.266828openalex-snapshot
ProfileMe: hardware support for instruction-level profiling on out-of-order processors
inferredcites →https://doi.org/10.5555/645989.674310openalex-snapshot
Quantifying instruction criticality
inferredcites →https://doi.org/10.5860/choice.49-3305openalex-snapshot
Data mining: concepts and techniques
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-72795-6_7openalex-snapshot
Impact of Performance Estimation on Fast Processor Simulators
inferred← citeshttps://doi.org/10.1007/978-3-319-39077-2_7openalex-snapshot
The Macro-DSE for HPC Processing Unit: The Physical Constraints Perspective
inferred← citeshttps://doi.org/10.1016/j.simpat.2016.08.006openalex-snapshot
Top-Down Characterization Approximation based on performance counters architecture for AMD processors
inferred← citeshttps://doi.org/10.1109/candar.2017.60openalex-snapshot
CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors
inferred← citeshttps://doi.org/10.1109/iccd53106.2021.00025openalex-snapshot
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end
inferred← citeshttps://doi.org/10.1109/ispass69572.2026.00042openalex-snapshot
FYI: A Foundational Counter Architecture for Building CPI Stacks on Out-of-Order Processors
inferred← citeshttps://doi.org/10.1109/lca.2017.2684813openalex-snapshot
Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors
inferred← citeshttps://doi.org/10.1109/lca.2024.3476909openalex-snapshot
GCStack: A GPU Cycle Accounting Mechanism for Providing Accurate Insight Into GPU Performance
inferred← citeshttps://doi.org/10.1109/mcsoc.2015.30openalex-snapshot
A Scalable and Fast Microprocessor Design Space Exploration Methodology
inferred← citeshttps://doi.org/10.1109/micro.2018.00054openalex-snapshot
RpStacks-MT: A High-Throughput Design Evaluation Methodology for Multi-Core Processors
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00208openalex-snapshot
Top-Down Microarchitecture Analysis Approximation Based on Performance Counter Architecture for SiFive RISC-V Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3311620openalex-snapshot
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
inferred← citeshttps://doi.org/10.1145/2872362.2872412openalex-snapshot
Analyzing Behavior Specialized Acceleration
inferred← citeshttps://doi.org/10.1145/2954679.2872412openalex-snapshot
Analyzing Behavior Specialized Acceleration
inferred← citeshttps://doi.org/10.1145/2954680.2872412openalex-snapshot
Analyzing Behavior Specialized Acceleration
inferred← citeshttps://doi.org/10.1145/2980024.2872412openalex-snapshot
Analyzing Behavior Specialized Acceleration
inferred← citeshttps://doi.org/10.1145/3590140.3629117openalex-snapshot
Fast, Light-weight, and Accurate Performance Evaluation using Representative Datacenter Behaviors
inferred← citeshttps://doi.org/10.1145/3727637openalex-snapshot
SnsBooster: Enhancing Sampling-based μ Arch Evaluation Efficiency through Online Performance Sensitivity Analysis
inferred← citeshttps://doi.org/10.1587/transfun.e102.a.758openalex-snapshot
Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution
inferred← citeshttps://doi.org/10.2197/ipsjjip.25.983openalex-snapshot
Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors
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