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Quantifying instruction criticality
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/hpca.2001.903262openalex-snapshot
Dynamic prediction of critical path instructions
inferredcites →https://doi.org/10.1109/iccd.1999.808593openalex-snapshot
The non-critical buffer: using load latency tolerance to improve data cache efficiency
inferredcites →https://doi.org/10.1109/icpp.1996.537165openalex-snapshot
PEWs: a decentralized dynamic scheduler for ILP processing
inferredcites →https://doi.org/10.1109/mascot.1994.284406openalex-snapshot
Near-critical path analysis of program activity graphs
inferredcites →https://doi.org/10.1109/micro.1998.742777openalex-snapshot
Load latency tolerance in dynamically scheduled processors
inferredcites →https://doi.org/10.1145/264107.264201openalex-snapshot
Complexity-effective superscalar processors
inferredcites →https://doi.org/10.1145/379240.379253openalex-snapshot
Focusing processor policies via critical-path prediction
inferredcites →https://doi.org/10.5555/563998.564013openalex-snapshot
Reducing power with dynamic critical path information
inferredcites →https://doi.org/10.5555/563998.564037openalex-snapshot
Dynamic speculative precomputation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11573937_6openalex-snapshot
Criticality Based Speculation Control for Speculative Multithreaded Architectures
inferred← citeshttps://doi.org/10.1007/11602569_7openalex-snapshot
Criticality Driven Energy Aware Speculation for Speculative Multithreaded Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-39304-4_2openalex-snapshot
Instruction Scheduling in Microprocessors
inferred← citeshttps://doi.org/10.1007/978-3-662-45815-0_3openalex-snapshot
HMCPA: Heuristic Method Utilizing Critical Path Analysis for Design Space Exploration of Superscalar Microprocessors
inferred← citeshttps://doi.org/10.1016/j.parco.2012.03.002openalex-snapshot
Criticality guided energy aware speculation for speculative multithreaded processors
inferred← citeshttps://doi.org/10.1049/iet-cdt.2013.0109openalex-snapshot
Column selection solutions for L 1 data caches implemented using eight‐transistor cells
inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.1109/adcom.2006.4289960openalex-snapshot
Selective Microarchitecture-Level Scaling for Energy Savings
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798280openalex-snapshot
Criticality-based optimizations for efficient load processing
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835952openalex-snapshot
Practical data value speculation for future high-end processors
inferred← citeshttps://doi.org/10.1109/iccd.2007.4601932openalex-snapshot
CAP: Criticality analysis for power-efficient speculative multithreading
inferred← citeshttps://doi.org/10.1109/icisip.2005.1529472openalex-snapshot
Applying perceptrons to computer architecture
inferred← citeshttps://doi.org/10.1109/ipdps49936.2021.00011openalex-snapshot
Dancing in the Dark: Profiling for Tiered Memory
inferred← citeshttps://doi.org/10.1109/isca.2018.00019openalex-snapshot
Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00018openalex-snapshot
Focused Value Prediction: Concepts, techniques and implementations presented in this paper are subject matter of pending patent applications, which have been filed by Intel Corporation
inferred← citeshttps://doi.org/10.1109/ispass.2006.1620788openalex-snapshot
Critical path analysis of the TRIPS architecture
inferred← citeshttps://doi.org/10.1109/micro.2014.26openalex-snapshot
RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
inferred← citeshttps://doi.org/10.1109/micro.2018.00054openalex-snapshot
RpStacks-MT: A High-Throughput Design Evaluation Methodology for Multi-Core Processors
inferred← citeshttps://doi.org/10.1109/micro.2018.00075openalex-snapshot
CritICs Critiquing Criticality in Mobile Apps
inferred← citeshttps://doi.org/10.1109/mm.2004.78openalex-snapshot
Interaction cost: for when event counts just don't add up
inferred← citeshttps://doi.org/10.1109/trustcom.2013.121openalex-snapshot
Quantitative Analysis of Inter-block Dependence in Speculative Execution
inferred← citeshttps://doi.org/10.1145/1013235.1013318openalex-snapshot
Application adaptive energy efficient clustered architectures
inferred← citeshttps://doi.org/10.1145/1022969.1022971openalex-snapshot
Interaction cost and shotgun profiling
inferred← citeshttps://doi.org/10.1145/1088149.1088163openalex-snapshot
Online performance analysis by statistical sampling of microprocessor performance counters
inferred← citeshttps://doi.org/10.1145/1356058.1356068openalex-snapshot
Accurate critical path prediction via random trace construction
inferred← citeshttps://doi.org/10.1145/1555754.1555800openalex-snapshot
End-to-end performance forecasting
inferred← citeshttps://doi.org/10.1145/1555815.1555800openalex-snapshot
End-to-end performance forecasting
inferred← citeshttps://doi.org/10.1145/1854273.1854308openalex-snapshot
Criticality-driven superscalar design space exploration
inferred← citeshttps://doi.org/10.1145/2609248.2609253openalex-snapshot
Exploiting critical data regions to reduce data cache energy consumption
inferred← citeshttps://doi.org/10.1145/2749469.2749470openalex-snapshot
Cost-effective speculative scheduling in high performance processors
inferred← citeshttps://doi.org/10.1145/2872887.2749470openalex-snapshot
Cost-effective speculative scheduling in high performance processors
inferred← citeshttps://doi.org/10.1145/3243176.3243208openalex-snapshot
Cost effective speculation with the omnipredictor
inferred← citeshttps://doi.org/10.1145/777412.777434openalex-snapshot
Quantifying instruction criticality for shared memory multiprocessors
inferred← citeshttps://doi.org/10.3929/ethz-b-000519275openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.48550/arxiv.2008.07171openalex-snapshot
CARGO : Context Augmented Critical Region Offload for Network-bound datacenter Workloads
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