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B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot
Effective hardware-based data prefetching for high-performance processors
inferredcites →https://doi.org/10.1109/c-m.1978.218016openalex-snapshot
Sequential Program Prefetching in Memory Hierarchies
inferredcites →https://doi.org/10.1109/hpca.2001.903271openalex-snapshot
Branch history guided instruction prefetching
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2005.13openalex-snapshot
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
inferredcites →https://doi.org/10.1109/hpca.2005.27openalex-snapshot
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
inferredcites →https://doi.org/10.1109/hpca.2008.4658627openalex-snapshot
PaCo: Probability-based path confidence prediction
inferredcites →https://doi.org/10.1109/hpca.2009.4798239openalex-snapshot
Practical off-chip meta-data for temporal memory streaming
inferredcites →https://doi.org/10.1109/iccd.1996.563561openalex-snapshot
Branch-directed and stride-based data cache prefetching
inferredcites →https://doi.org/10.1109/iccd.1997.628926openalex-snapshot
Instruction prefetching using branch prediction information
inferredcites →https://doi.org/10.1109/isca.2002.1003587openalex-snapshot
Design tradeoffs for the alpha EV8 conditional branch predictor
inferredcites →https://doi.org/10.1109/ispass.2006.1620802openalex-snapshot
Friendly fire: understanding the effects of multiprocessor prefetches
inferredcites →https://doi.org/10.1109/jssc.1974.1050511openalex-snapshot
Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/micro.1996.566463openalex-snapshot
Tango: a hardware-based data prefetching technique for superscalar processors
inferredcites →https://doi.org/10.1109/micro.2008.4771774openalex-snapshot
Temporal instruction fetch streaming
inferredcites →https://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferredcites →https://doi.org/10.1109/mm.2012.17openalex-snapshot
Dark Silicon and the End of Multicore Scaling
inferredcites →https://doi.org/10.1109/sbac-pad.2009.17openalex-snapshot
Composite Confidence Estimators for Enhanced Speculation Control
inferredcites →https://doi.org/10.1145/1555754.1555766openalex-snapshot
Spatio-temporal memory streaming
inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
inferredcites →https://doi.org/10.1145/2540708.2540730openalex-snapshot
Linearizing irregular memory accesses for improved correlated prefetching
inferredcites →https://doi.org/10.1145/2591635.2667173openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/263580.263597openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/291069.291034openalex-snapshot
Dependence based prefetching for linked data structures
inferredcites →https://doi.org/10.1145/545214.545249openalex-snapshot
Design tradeoffs for the Alpha EV8 conditional branch predictor
inferredcites →https://doi.org/10.5555/320080.320085openalex-snapshot
Fetch directed instruction prefetching
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/bs.adcom.2021.11.003openalex-snapshot
Introduction to data prefetching
inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.1109/hpca.2018.00021openalex-snapshot
Domino Temporal Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca.2019.00053openalex-snapshot
Bingo Spatial Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca.2019.00064openalex-snapshot
R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408449openalex-snapshot
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00018openalex-snapshot
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches
inferred← citeshttps://doi.org/10.1109/isca.2018.00020openalex-snapshot
Rethinking Belady's Algorithm to Accommodate Prefetching
inferred← citeshttps://doi.org/10.1109/ispass.2017.7975288openalex-snapshot
Prefetching for cloud workloads: An analysis based on address patterns
inferred← citeshttps://doi.org/10.1109/lca.2018.2847345openalex-snapshot
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/micro.2016.7783704openalex-snapshot
Dictionary sharing: An efficient cache compression scheme for compressed caches
inferred← citeshttps://doi.org/10.1109/micro.2016.7783763openalex-snapshot
Path confidence based lookahead prefetching
inferred← citeshttps://doi.org/10.1109/tc.2016.2547392openalex-snapshot
SPAC:A Synergistic Prefetcher Aggressiveness Controller for Multi-core Systems
inferred← citeshttps://doi.org/10.1145/2830772.2830816openalex-snapshot
Self-contained, accurate precomputation prefetching
inferred← citeshttps://doi.org/10.1145/2830772.2830831openalex-snapshot
The inner most loop iteration counter
inferred← citeshttps://doi.org/10.1145/2890505openalex-snapshot
Thread-Aware Adaptive Prefetcher on Multicore Systems
inferred← citeshttps://doi.org/10.1145/2907071openalex-snapshot
A Survey of Recent Prefetching Techniques for Processor Caches
inferred← citeshttps://doi.org/10.1145/3132402.3132409openalex-snapshot
Speculative paging for future NVM storage
inferred← citeshttps://doi.org/10.1145/3307650.3322207openalex-snapshot
Perceptron-based prefetch filtering
inferred← citeshttps://doi.org/10.1145/3312740openalex-snapshot
Evaluation of Hardware Data Prefetchers on Server Processors
inferred← citeshttps://doi.org/10.1145/3419973openalex-snapshot
Highly Concurrent Latency-tolerant Register Files for GPUs
inferred← citeshttps://doi.org/10.1145/3452099openalex-snapshot
Fast Key-Value Lookups with Node Tracker
inferred← citeshttps://doi.org/10.1145/3466752.3480114openalex-snapshot
Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning
inferred← citeshttps://doi.org/10.1145/3633461openalex-snapshot
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems
inferred← citeshttps://doi.org/10.1145/3762997openalex-snapshot
Augur: Semantics-Aware Temporal Prefetching for Linked Data Structure
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3853411/v1openalex-snapshot
DMDP: A Dynamic Multi-Delta Prefetcher with Customizable Runtime Quality-Aware Feedback
inferred← citeshttps://doi.org/10.32657/10356/72031openalex-snapshot
Usage-pattern-based scheduling schemes for power optimization in multi-core systems
inferred← citeshttps://doi.org/10.3929/ethz-b-000519275openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.48550/arxiv.2005.06102openalex-snapshot
Semantic prefetching using forecast slices
inferred← citeshttps://doi.org/10.48550/arxiv.2009.00715openalex-snapshot
A Survey on Recent Hardware Data Prefetching Approaches with An Emphasis on Servers
inferred← citeshttps://doi.org/10.48550/arxiv.2010.09330openalex-snapshot
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
inferred← citeshttps://doi.org/10.5555/3195638.3195711openalex-snapshot
Path confidence based lookahead prefetching
inferred← citeshttps://doi.org/10.70675/c7c2b786z3986z4edez945fzcd4d3a382f16openalex-snapshot
Exploiting heterogeneous many cores on sequential code
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