On the public citation graph
An interconnect architecture for networking systems on chips
0 signed · 251 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/35.668286openalex-snapshot
Beyond best effort: router architectures for the differentiated services of tomorrow's Internet
inferredcites →https://doi.org/10.1109/40.612211openalex-snapshot
AMBA: enabling reusable on-chip designs
inferredcites →https://doi.org/10.1109/49.76643openalex-snapshot
Throughput analysis, optimal buffer allocation, and traffic imbalance study of a generic nonblocking packet switch
inferredcites →https://doi.org/10.1109/iccad.2000.896509openalex-snapshot
Efficient exploration of the SoC communication architecture design space
inferredcites →https://doi.org/10.1109/icvd.2001.902636openalex-snapshot
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures
inferredcites →https://doi.org/10.1145/285237.285283openalex-snapshot
High-speed policy-based packet forwarding using efficient multi-dimensional range matching
inferredcites →https://doi.org/10.1145/285243.285283openalex-snapshot
High-speed policy-based packet forwarding using efficient multi-dimensional range matching
inferredcites →https://doi.org/10.1145/288548.289067openalex-snapshot
Communication synthesis for distributed embedded systems
inferredcites →https://doi.org/10.1145/298865.298866openalex-snapshot
Bus-based communication synthesis on system level
inferredcites →https://doi.org/10.1145/337292.337561openalex-snapshot
Communication architecture tuners
inferredcites →https://doi.org/10.21236/ada416530openalex-snapshot
Communication Synthesis for Distributed Embedded Systems
inferredcites →https://doi.org/10.5555/602902.602998openalex-snapshot
Efficient exploration of the SoC communication architecture design space
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.3217/jucs-011-06-0944openalex-extracted
On Complexity of Collective Communications on a Fat Cube Topology
inferred← citeshttps://doi.org/10.5281/zenodo.1073557openalex-extracted
Pipelined Control-Path Effects On Area And Performance Of A Wormhole-Switched Network-On-Chip
inferred← citeshttps://doi.org/10.5281/zenodo.1079657openalex-extracted
Flexible Wormhole-Switched Network-On-Chip With Two-Level Priority Data Delivery Service
inferred← citeshttps://doi.org/10.1002/cta.662openalex-snapshot
Improving Networks‐on‐Chip performability: A topology‐based approach
inferred← citeshttps://doi.org/10.1002/tee.21921openalex-snapshot
Power analysis for asynchronous network‐on‐chip
inferred← citeshttps://doi.org/10.1002/tee.22678openalex-snapshot
Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm
inferred← citeshttps://doi.org/10.1007/0-387-28327-7_19openalex-snapshot
Optimizing Communication Architectures for Parallel Embedded Systems
inferred← citeshttps://doi.org/10.1007/1-4020-3454-7_1openalex-snapshot
Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip
inferred← citeshttps://doi.org/10.1007/1-4020-8149-9_31openalex-snapshot
The Implications of Real-Time Behavior in Networks-on-Chip Architectures
inferred← citeshttps://doi.org/10.1007/978-0-387-73661-7_13openalex-snapshot
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping
inferred← citeshttps://doi.org/10.1007/978-0-387-89558-1_7openalex-snapshot
QoS in Networks-on-Chip – Beyond Priority and Circuit Switching Techniques
inferred← citeshttps://doi.org/10.1007/978-1-4020-6488-3_12openalex-snapshot
xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
inferred← citeshttps://doi.org/10.1007/978-1-4614-4274-5_2openalex-snapshot
NoC Modeling and Topology Exploration
inferred← citeshttps://doi.org/10.1007/978-1-4614-9405-8_3openalex-snapshot
Fast Network-on-Chip Design
inferred← citeshttps://doi.org/10.1007/978-3-030-65407-8_14openalex-snapshot
An Overview of Multicast Routing Algorithms in Network on Chip
inferred← citeshttps://doi.org/10.1007/978-3-319-25766-2_5openalex-snapshot
Synchronous and Asynchronous NoC Design Under High Process Variation
inferred← citeshttps://doi.org/10.1007/978-3-319-32467-8_61openalex-snapshot
Design of a Deadlock-Free XY-YX Router for Network-on-Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-30494-4_5openalex-snapshot
A Functional Approach to the Formal Specification of Networks on Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-74784-0_41openalex-snapshot
The SKB: A Semi-Completely-Connected Bus for On-Chip Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-13119-6_14openalex-snapshot
Network-on-Chip Routing Algorithms by Breaking Cycles
inferred← citeshttps://doi.org/10.1007/978-3-642-15672-4_37openalex-snapshot
A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoC
inferred← citeshttps://doi.org/10.1007/978-3-642-17857-3_10openalex-snapshot
FIFO Optimization for Energy-Performance Trade-off in Mesh-of-Tree Based Network-on-Chip
inferred← citeshttps://doi.org/10.1007/978-981-15-8135-9_6openalex-snapshot
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks
inferred← citeshttps://doi.org/10.1007/978-981-99-1472-2_15openalex-snapshot
FPGA Implementations and Performance Analysis of Different Routing Algorithms for the 2D-Mesh Network-On-Chip
inferred← citeshttps://doi.org/10.1007/s00165-007-0049-0openalex-snapshot
A functional formalization of on chip communications
inferred← citeshttps://doi.org/10.1007/s10766-008-0081-6openalex-snapshot
A Flexible Framework for Communication Evaluation in SoC Design
inferred← citeshttps://doi.org/10.1007/s10836-019-05792-1openalex-snapshot
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip
inferred← citeshttps://doi.org/10.1007/s10836-020-05878-1openalex-snapshot
Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks
inferred← citeshttps://doi.org/10.1007/s11227-014-1178-xopenalex-snapshot
A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures
inferred← citeshttps://doi.org/10.1007/s11235-008-9077-1openalex-snapshot
An interconnection architecture for network-on-chip systems
inferred← citeshttps://doi.org/10.1007/s11277-013-1257-yopenalex-snapshot
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
inferred← citeshttps://doi.org/10.1007/s11277-018-5376-3openalex-snapshot
Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication
inferred← citeshttps://doi.org/10.1007/s11704-010-0117-0openalex-snapshot
An analytical model for Network-on-Chip with finite input buffer
inferred← citeshttps://doi.org/10.1007/s40031-022-00735-5openalex-snapshot
Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections
inferred← citeshttps://doi.org/10.1016/j.mejo.2011.10.002openalex-snapshot
Asynchronous switching for low-power networks-on-chip
inferred← citeshttps://doi.org/10.1016/j.micpro.2008.08.004openalex-snapshot
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
inferred← citeshttps://doi.org/10.1016/j.micpro.2009.03.002openalex-snapshot
Power optimization for application-specific networks-on-chips: A topology-based approach
inferred← citeshttps://doi.org/10.1016/j.micpro.2010.10.001openalex-snapshot
Virtualizing network-on-chip resources in chip-multiprocessors
inferred← citeshttps://doi.org/10.1016/j.micpro.2011.08.013openalex-snapshot
A reconfigurable computing platform for real time embedded applications
inferred← citeshttps://doi.org/10.1016/j.micpro.2012.05.012openalex-snapshot
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.02.003openalex-snapshot
Traffic engineered NoC for streaming applications
inferred← citeshttps://doi.org/10.1016/j.parco.2006.09.003openalex-snapshot
The psi-cube: a bus-based cube-type clustering network for high-performance on-chip systems
inferred← citeshttps://doi.org/10.1016/j.proeng.2012.01.423openalex-snapshot
The Design and Implementation of a Hierarchical Networkon-Chip
inferred← citeshttps://doi.org/10.1016/j.simpat.2010.10.008openalex-snapshot
Performance evaluation and design tradeoffs of on-chip interconnect architectures
inferred← citeshttps://doi.org/10.1016/j.suscom.2019.06.005openalex-snapshot
The MPEG-4 based energy efficient application traffic modelling and synthesis for network-on-chip architecture
inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.10.003openalex-snapshot
A monitoring-aware network-on-chip design flow
inferred← citeshttps://doi.org/10.1016/j.sysarc.2009.07.002openalex-snapshot
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
inferred← citeshttps://doi.org/10.1016/j.sysarc.2009.10.002openalex-snapshot
An analytical performance model for the Spidergon NoC with virtual channels
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.10.002openalex-snapshot
3D network-on-chip design for embedded ubiquitous computing systems
inferred← citeshttps://doi.org/10.1016/j.vlsi.2004.03.003openalex-snapshot
HERMES: an infrastructure for low area overhead packet-switching networks on chip
inferred← citeshttps://doi.org/10.1016/j.vlsi.2014.10.006openalex-snapshot
High Throughput Asynchronous NoC Design under High Process Variation
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.02.001openalex-snapshot
Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services
inferred← citeshttps://doi.org/10.1016/j.vlsi.2021.08.005openalex-snapshot
An energy efficient synthesis flow for application specific SoC design
inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.06.014openalex-snapshot
FRDS: An efficient unique on-Chip interconnection network architecture
inferred← citeshttps://doi.org/10.1016/j.vlsi.2025.102529openalex-snapshot
A survey on vertical interconnection and topology of three-dimensional network-on-chip
inferred← citeshttps://doi.org/10.1016/s1005-8885(08)60273-3openalex-snapshot
S-Mesh: a Mesh-based on-chip network with separation of control and transmission
inferred← citeshttps://doi.org/10.1088/1742-6596/1921/1/012075openalex-snapshot
Design of Network on Chip (NoC) Computing Node for Mesh Topology using Soft-core NIOS-II Processor
inferred← citeshttps://doi.org/10.1109/aina.2007.31openalex-snapshot
An Analytical Performance Model for the Spidergon NoC
inferred← citeshttps://doi.org/10.1109/aina.2007.98openalex-snapshot
On Quantifying Fault Patterns of the Mesh Interconnect Networks
inferred← citeshttps://doi.org/10.1109/aina.2008.142openalex-snapshot
Modeling Differentiated Services-Based QoS in Wormhole-Routed NoCs
inferred← citeshttps://doi.org/10.1109/artcom.2009.164openalex-snapshot
A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic
inferred← citeshttps://doi.org/10.1109/asap.2008.4580155openalex-snapshot
A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems
inferred← citeshttps://doi.org/10.1109/aspdac.2005.1466498openalex-snapshot
A flexible framework for communication evaluation in SoC design
inferred← citeshttps://doi.org/10.1109/ccca.2011.6031404openalex-snapshot
Network interface sharing for SoCs based NoC
inferred← citeshttps://doi.org/10.1109/ccece.2007.240openalex-snapshot
Introducing OperaNP: A Reconfigurable NoC-Based Platform
inferred← citeshttps://doi.org/10.1109/ccece.2008.4564530openalex-snapshot
Early performance estimation in wormhole-switched Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/ccece.2008.4564695openalex-snapshot
High-level specification and logic implementation of single-chip multiprocessor systems based on a configurable router
inferred← citeshttps://doi.org/10.1109/cec.2009.4983144openalex-snapshot
Parallel BMDA with an aggregation of probability models
inferred← citeshttps://doi.org/10.1109/cict.2013.6558214openalex-snapshot
Area and power efficient network on chip router architecture
inferred← citeshttps://doi.org/10.1109/conecct.2015.7383943openalex-snapshot
Routing solution over a multi-layered Network on Chip
inferred← citeshttps://doi.org/10.1109/date.2004.1268998openalex-snapshot
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
inferred← citeshttps://doi.org/10.1109/date.2004.1268999openalex-snapshot
×pipesCompiler: a tool for instantiating application specific networks on chip
inferred← citeshttps://doi.org/10.1109/date.2008.4484869openalex-snapshot
Multicast Parallel Pipeline Router Architecture for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/date.2012.6176709openalex-snapshot
A fast, source-synchronous ring-based network-on-chip design
inferred← citeshttps://doi.org/10.1109/dsd.2003.1231894openalex-snapshot
NoCs: a new contract between hardware and software
inferred← citeshttps://doi.org/10.1109/dsd.2003.1231983openalex-snapshot
A methodology for designing communication architectures for multiprocessor SoCs
inferred← citeshttps://doi.org/10.1109/dsd.2006.11openalex-snapshot
A Monitoring-Aware Network-on-Chip Design Flow
inferred← citeshttps://doi.org/10.1109/dsd.2007.4341445openalex-snapshot
An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models
inferred← citeshttps://doi.org/10.1109/dsd.2007.4341515openalex-snapshot
On network-on-chip comparison
inferred← citeshttps://doi.org/10.1109/dsd.2010.46openalex-snapshot
A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism
inferred← citeshttps://doi.org/10.1109/eait.2012.6408020openalex-snapshot
Network-on-chip routing using Structural Diametrical 2D mesh architecture
inferred← citeshttps://doi.org/10.1109/electro.2009.5441156openalex-snapshot
Performance evaluation of Network on Chip architectures
inferred← citeshttps://doi.org/10.1109/fpl.2005.1515738openalex-snapshot
Gals systems prototyping using multiclock fpgas and asynchronous network-on-chips
inferred← citeshttps://doi.org/10.1109/fpl.2007.4380761openalex-snapshot
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2002.1188658openalex-snapshot
FPGAs as meta-platforms for embedded systems
inferred← citeshttps://doi.org/10.1109/hldvt.2004.1431260openalex-snapshot
An event-based network-on-chip monitoring service
inferred← citeshttps://doi.org/10.1109/hpcc.2012.78openalex-snapshot
Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach
inferred← citeshttps://doi.org/10.1109/icacc.2011.6016470openalex-snapshot
Design of a Crosspoint Queued router for a micro-network in SoCs
inferred← citeshttps://doi.org/10.1109/icasic.2007.4415871openalex-snapshot
Simulation and performance analysis of network on chip architectures using OPNET
inferred← citeshttps://doi.org/10.1109/iccica52458.2021.9697123openalex-snapshot
Energy Performance of Network on Chip Architecture for Rectangular Perfect Difference Network Topology
inferred← citeshttps://doi.org/10.1109/iccsit.2009.5234772openalex-snapshot
A partially adaptive routing algorithm for Benes network on chip
inferred← citeshttps://doi.org/10.1109/iceac.2012.6471021openalex-snapshot
Redundancy and ECC mechanisms to improve energy efficiency of on-die interconnects
inferred← citeshttps://doi.org/10.1109/icecs.2009.5410930openalex-snapshot
Power efficient Networks on Chip
inferred← citeshttps://doi.org/10.1109/icecs.2009.5410933openalex-snapshot
High Throughput architecture for OCTAGON Network on Chip
inferred← citeshttps://doi.org/10.1109/icepe50861.2021.9404379openalex-snapshot
Design of High Performance HMRPD Network on Chip Interconnect for Neuromorphic Architectures
inferred← citeshttps://doi.org/10.1109/iciinfs.2008.4798389openalex-snapshot
Mesh-of-Tree Based Scalable Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/icn.2007.67openalex-snapshot
Optimum Topology-Aware Scheduling of Many-to-Many Collective Communications
inferred← citeshttps://doi.org/10.1109/icniconsmcl.2006.169openalex-snapshot
Performance of Collective Communications on Interconnection Networks with Fat nodes and Edges
inferred← citeshttps://doi.org/10.1109/icpads.2007.4447826openalex-snapshot
Analytical modelling of communication in the rectangular mesh NoC
inferred← citeshttps://doi.org/10.1109/icpp.2007.28openalex-snapshot
Communication Modelling of the Spidergon NoC with Virtual Channels
inferred← citeshttps://doi.org/10.1109/icsict.2008.4734937openalex-snapshot
Design and analysis of on-chip router
inferred← citeshttps://doi.org/10.1109/icspcc.2014.6986289openalex-snapshot
Square-Octagon interconnection architecture for Network-on-chips
inferred← citeshttps://doi.org/10.1109/ictta.2004.1307937openalex-snapshot
Formal design and verification of on chip networking
inferred← citeshttps://doi.org/10.1109/idt.2007.4437429openalex-snapshot
A Topology-based Design Methodology for Networks-on-Chip Applications
inferred← citeshttps://doi.org/10.1109/idt.2007.4437466openalex-snapshot
Performance Analysis of Networks-on-Chip Routers
inferred← citeshttps://doi.org/10.1109/idt.2009.5404136openalex-snapshot
A delay-aware topology-based design for Networks-on-Chip applications
inferred← citeshttps://doi.org/10.1109/idt.2011.6123102openalex-snapshot
Layout-aware high performance interconnects for Network-on-Chip design in deep nanometer technologies
inferred← citeshttps://doi.org/10.1109/ies.2006.357464openalex-snapshot
Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective
inferred← citeshttps://doi.org/10.1109/impact.2011.6117292openalex-snapshot
Fault-tolerant mesh for 3D network on chip
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536513openalex-snapshot
Flexible parallel pipeline network-on-chip based on dynamic packet identity management
inferred← citeshttps://doi.org/10.1109/ipdps.2009.5161210openalex-snapshot
Design and implementation of the Quarc Network on-Chip
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470784openalex-snapshot
Analytical performance comparison of 2D Mesh, WK-recursive, and Spidergon NoCs
inferred← citeshttps://doi.org/10.1109/iscas.2005.1465352openalex-snapshot
A ns-2 Simulator Utilizing Chaotic Maps for Network-on-Chip Traffic Analysis
inferred← citeshttps://doi.org/10.1109/iscas.2006.1693001openalex-snapshot
NoC Monitoring: Impact on the Design Flow
inferred← citeshttps://doi.org/10.1109/iscas.2007.378193openalex-snapshot
Programmable Routing Tables for Degradable Torus-Based Networks on Chips
inferred← citeshttps://doi.org/10.1109/iscas.2007.378473openalex-snapshot
Binary-Truncated CDMA-Based On-Chip Network
inferred← citeshttps://doi.org/10.1109/iscas.2009.5118244openalex-snapshot
High throughput architecture for high performance NoC
inferred← citeshttps://doi.org/10.1109/iscas.2010.5537665openalex-snapshot
A low-latency NoC router with lookahead bypass
inferred← citeshttps://doi.org/10.1109/iscas.2010.5537753openalex-snapshot
Power characteristics of Networks on Chip
inferred← citeshttps://doi.org/10.1109/iscas.2010.5537922openalex-snapshot
Asynchronous BFT for low power networks on chip
inferred← citeshttps://doi.org/10.1109/ised.2012.68openalex-snapshot
SD2D: A Novel Routing Architecture for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/isocc.2012.6407066openalex-snapshot
Hybrid Mesh-Ring wireless Network on Chip for multi-core system
inferred← citeshttps://doi.org/10.1109/ispa.2008.123openalex-snapshot
Mesh Connected Crossbars: A Novel NoC Topology with Scalable Communication Bandwidth
inferred← citeshttps://doi.org/10.1109/issoc.2005.1595630openalex-snapshot
Network-on-Chip: A New Paradigm for System-on-Chip Design
inferred← citeshttps://doi.org/10.1109/issoc.2006.321981openalex-snapshot
Evaluation of current QoS Mechanisms in Networks on Chip
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00044openalex-snapshot
Locating Open-Channels in Octagon Networks on Chip-Microprocessors
inferred← citeshttps://doi.org/10.1109/iwsoc.2005.98openalex-snapshot
Simulation and analysis of network on chip architecture for wireless communication system
inferred← citeshttps://doi.org/10.1109/iwsoc.2006.348272openalex-snapshot
A Delay Model for Networks-on-Chip Output-Queuing Router
inferred← citeshttps://doi.org/10.1109/lisat.2012.6223200openalex-snapshot
CLICHE network on chip: A novel multichannel acquisition module for a high throughput architecture
inferred← citeshttps://doi.org/10.1109/mdt.2005.108openalex-snapshot
Design, Synthesis, and Test of Networks on Chips
inferred← citeshttps://doi.org/10.1109/naecon.2012.6531030openalex-snapshot
Octagon architecture for low power and high performance NoC design
inferred← citeshttps://doi.org/10.1109/newcas.2008.4606312openalex-snapshot
Implementation of a configurable router for embedded network-on-chip support in FPGAs
inferred← citeshttps://doi.org/10.1109/nocs.2007.1openalex-snapshot
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
inferred← citeshttps://doi.org/10.1109/norchp.2008.4738319openalex-snapshot
High Throughput High Performance NoC Switch
inferred← citeshttps://doi.org/10.1109/parelec.2006.25openalex-snapshot
Complexity of Collective Communications on NoCs
inferred← citeshttps://doi.org/10.1109/sbcci.2003.1232824openalex-snapshot
SoCIN: a parametric and scalable network-on-chip
inferred← citeshttps://doi.org/10.1109/socc.2011.6085125openalex-snapshot
Power characteristics of Asynchronous Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/soccon.2009.5398069openalex-snapshot
High throughput architecture for CLICHÉ Network on Chip
inferred← citeshttps://doi.org/10.1109/socdc.2008.4815587openalex-snapshot
Design ASNoC for low-power SoCs
inferred← citeshttps://doi.org/10.1109/spl.2008.4547735openalex-snapshot
Simulation-Based Approach for Evaluating On-Chip Interconnect Architectures
inferred← citeshttps://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferred← citeshttps://doi.org/10.1109/tc.2012.126openalex-snapshot
Efficient All-to-All Broadcast in Gaussian On-Chip Networks
inferred← citeshttps://doi.org/10.1109/tcad.2004.839493openalex-snapshot
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration
inferred← citeshttps://doi.org/10.1109/tcad.2004.841866openalex-snapshot
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors
inferred← citeshttps://doi.org/10.1109/tcad.2017.2693263openalex-snapshot
Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS
inferred← citeshttps://doi.org/10.1109/tencon.2007.4428942openalex-snapshot
Simulation and performance evaluation for network on chip design using OPNET
inferred← citeshttps://doi.org/10.1109/tencon50793.2020.9293760openalex-snapshot
Adaptive BFS Based Fault Tolerant Routing Algorithm for Network on Chip
inferred← citeshttps://doi.org/10.1109/tpds.2008.106openalex-snapshot
Application Specific Routing Algorithms for Networks on Chip
inferred← citeshttps://doi.org/10.1109/tpds.2013.121openalex-snapshot
A Decision Procedure for Deadlock-Free Routing in Wormhole Networks
inferred← citeshttps://doi.org/10.1109/tpds.2015.2390631openalex-snapshot
MACS: A Highly Customizable Low-Latency Communication Architecture
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000727openalex-snapshot
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2019758openalex-snapshot
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2296742openalex-snapshot
A Systematic Design Methodology for Low-Power NoCs
inferred← citeshttps://doi.org/10.1109/vlsi.design.2009.55openalex-snapshot
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration
inferred← citeshttps://doi.org/10.1109/vlsisoc.2007.4402487openalex-snapshot
Rate-based scheduling policy for QoS flows in networks on chip
inferred← citeshttps://doi.org/10.1109/vlsisoc.2009.6041351openalex-snapshot
A study on WK-recursive topology using gpNoCsim++ simulator and comparison to Other topologies
inferred← citeshttps://doi.org/10.1109/waina.2008.230openalex-snapshot
An Adaptive Software-Based Deadlock Recovery Technique
inferred← citeshttps://doi.org/10.1142/s0129626408003363openalex-snapshot
ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE
inferred← citeshttps://doi.org/10.1142/s0218126611008018openalex-snapshot
RQRT: REDUCE QUERYING ROUTING TABLE FOR MESH-BASED NETWORK-ON-CHIP
inferred← citeshttps://doi.org/10.1145/1109118.1109126openalex-snapshot
An event-based monitoring service for networks on chip
inferred← citeshttps://doi.org/10.1145/1120725.1120766openalex-snapshot
A flexible framework for communication evaluation in SoC design
inferred← citeshttps://doi.org/10.1145/1132952.1132953openalex-snapshot
A survey of research and practices of Network-on-chip
inferred← citeshttps://doi.org/10.1145/1151074.1151076openalex-snapshot
A design methodology for application-specific networks-on-chip
inferred← citeshttps://doi.org/10.1145/1217975.1217985openalex-snapshot
Towards a formal theory of on chip communications in the ACL2 logic
inferred← citeshttps://doi.org/10.1145/1276958.1277358openalex-snapshot
An evolutionary approach to collective communication scheduling
inferred← citeshttps://doi.org/10.1145/1284480.1284515openalex-snapshot
Router architecture for high-performance NoCs
inferred← citeshttps://doi.org/10.1145/1366110.1366191openalex-snapshot
Mesh-of-tree deterministic routing for network-on-chip architecture
inferred← citeshttps://doi.org/10.1145/1389095.1389391openalex-snapshot
An evolutionary design technique for collective communications on optimal diameter-degree networks
inferred← citeshttps://doi.org/10.1145/1403375.1403714openalex-snapshot
Multicast parallel pipeline router architecture for network-on-chip
inferred← citeshttps://doi.org/10.1145/1404371.1404421openalex-snapshot
Executable formal specification and validation of NoC communication infrastructures
inferred← citeshttps://doi.org/10.1145/1569901.1570107openalex-snapshot
Evolutionary optimization of multistage interconnection networks performance
inferred← citeshttps://doi.org/10.1145/1830483.1830698openalex-snapshot
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
inferred← citeshttps://doi.org/10.1145/1999946.1999951openalex-snapshot
Automatic verification for deadlock in Networks-on-Chips with adaptive routing and wormhole switching
inferred← citeshttps://doi.org/10.1145/2786572.2786581openalex-snapshot
An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links
inferred← citeshttps://doi.org/10.1145/3291532openalex-snapshot
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
inferred← citeshttps://doi.org/10.1155/2007/97929openalex-snapshot
A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis
inferred← citeshttps://doi.org/10.1155/2009/548324openalex-snapshot
A Formal Approach to the Verification of Networks on Chip
inferred← citeshttps://doi.org/10.1155/2009/941701openalex-snapshot
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management
inferred← citeshttps://doi.org/10.11606/d.3.2016.tde-31122015-101031openalex-snapshot
DyAFNoC: sistema dinamicamente reconfigurável baseado em redes intrachip com algoritmo de roteamento ordenado por dimensão flexibilizado.
inferred← citeshttps://doi.org/10.11648/j.ajnc.s.2015040301.11openalex-snapshot
C2 Torus New Interconnection Network Topology Based on 2D Torus
inferred← citeshttps://doi.org/10.1186/1687-3963-2007-097929openalex-snapshot
A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis
inferred← citeshttps://doi.org/10.1201/9781315216072openalex-snapshot
Network-on-Chip: The Next Generation of System-on-Chip Integration
inferred← citeshttps://doi.org/10.1201/9781315216072-2openalex-snapshot
Interconnection Networks in Network-on-Chip
inferred← citeshttps://doi.org/10.1201/b17748-3openalex-snapshot
Interconnection Networks in Network-on-Chip
inferred← citeshttps://doi.org/10.12928/telkomnika.v13i1.1262openalex-snapshot
Topology Architecture and Routing Algorithms of Octagon-Connected Torus Interconnection Network
inferred← citeshttps://doi.org/10.1360/n112018-00009openalex-snapshot
Design of communication architecture for flexible electronic system based on honeycomb
inferred← citeshttps://doi.org/10.14257/ijfgcn.2016.9.9.16openalex-snapshot
A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks
inferred← citeshttps://doi.org/10.1504/ijcse.2017.10003830openalex-snapshot
A high-level exploration tool for three-dimensional network-on-chip
inferred← citeshttps://doi.org/10.1504/ijhpsa.2008.021797openalex-snapshot
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
inferred← citeshttps://doi.org/10.15680/ijirset.2013.0208077openalex-snapshot
Design and Analysis of Synchronous Look-Ahead Routing Computation using XY, Adaptive XY, and Dimension-Order Algorithms for the 2D-Mesh Topology
showing the first 200 of 234 · page through all 234
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.