On the public citation graph
Bobcat: AMD's Low-Power x86 Processor
0 signed · 28 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/mm.2003.1196116openalex-snapshot
The AMD opteron processor for multiprocessor servers
inferredcites →https://doi.org/10.1109/tc.2008.203openalex-snapshot
Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.parco.2017.01.003openalex-snapshot
TCASM: An asynchronous shared memory interface for high-performance application composition
inferred← citeshttps://doi.org/10.1109/access.2021.3126739openalex-snapshot
Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection
inferred← citeshttps://doi.org/10.1109/arith.2013.24openalex-snapshot
The Floating-Point Unit of the Jaguar x86 Core
inferred← citeshttps://doi.org/10.1109/date.2012.6176483openalex-snapshot
Run-time power-gating in caches of GPUs for leakage energy savings
inferred← citeshttps://doi.org/10.1109/dsd.2011.98openalex-snapshot
Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors
inferred← citeshttps://doi.org/10.1109/iccd.2011.6081388openalex-snapshot
Thread-aware dynamic shared cache compression in multi-core processors
inferred← citeshttps://doi.org/10.1109/isca.2012.6237036openalex-snapshot
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557152openalex-snapshot
Evaluating cache coherent shared virtual memory for heterogeneous multicore chips
inferred← citeshttps://doi.org/10.1109/mm.2012.23openalex-snapshot
FabScalar: Automating Superscalar Core Design
inferred← citeshttps://doi.org/10.1109/mm.2021.3115616openalex-snapshot
What Made Us Stronger: An Inside Look Back at the History of AMD Microprocessor Development
inferred← citeshttps://doi.org/10.1109/sbac-pad.2014.39openalex-snapshot
Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores
inferred← citeshttps://doi.org/10.1109/tc.2014.2361526openalex-snapshot
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching
inferred← citeshttps://doi.org/10.1109/tcad.2022.3216549openalex-snapshot
Benchmarking of Machine Learning Methods for Multiscale Thermal Simulation of Integrated Circuits
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2284281openalex-snapshot
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2293422openalex-snapshot
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2012.6379024openalex-snapshot
A physical design study of fabscalar-generated superscalar cores
inferred← citeshttps://doi.org/10.1145/2155620.2155662openalex-snapshot
A register-file approach for row buffer caches in die-stacked DRAMs
inferred← citeshttps://doi.org/10.1145/2333660.2333745openalex-snapshot
The core-C6 (CC6) sleep state of the AMD bobcat x86 microprocessor
inferred← citeshttps://doi.org/10.1145/2451916.2451923openalex-snapshot
High performance and low power design techniques for ASIC and custom in nanometer technologies
inferred← citeshttps://doi.org/10.1145/3613424.3623774openalex-snapshot
Branch Target Buffer Organizations
inferred← citeshttps://doi.org/10.1201/9780429171529-24openalex-snapshot
Multicore Architectures and Their Software Landscape
inferred← citeshttps://doi.org/10.5555/2492708.2492783openalex-snapshot
Run-time power-gating in caches of GPUs for leakage energy savings
inferred← citeshttps://doi.org/10.70675/c7c2b786z3986z4edez945fzcd4d3a382f16openalex-snapshot
Exploiting heterogeneous many cores on sequential code
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.