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Control-Flow Decoupling

https://doi.org/10.1109/micro.2012.38
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hicss.1993.270622openalex-snapshot
The NSR processor
inferredcites →https://doi.org/10.1109/hpca.1997.569617openalex-snapshot
Architectural support for compiler-synthesized dynamic branch prediction strategies: Rationale and initial results
inferredcites →https://doi.org/10.1109/hpca.2001.903250openalex-snapshot
Speculative data-driven multithreading
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2007.346186openalex-snapshot
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
inferredcites →https://doi.org/10.1109/iccd.1999.808579openalex-snapshot
Dynamic branch decoupled architecture
inferredcites →https://doi.org/10.1109/iiswc.2006.302743openalex-snapshot
MineBench: A Benchmark Suite for Data Mining Workloads
inferredcites →https://doi.org/10.1109/isca.1999.765950openalex-snapshot
Simultaneous subordinate microthreading (SSMT)
inferredcites →https://doi.org/10.1109/isca.2001.937426openalex-snapshot
Execution-based prediction using speculative slices
inferredcites →https://doi.org/10.1109/isca.2002.1003588openalex-snapshot
Difficult-path branch prediction using subordinate microthreads
inferredcites →https://doi.org/10.1109/ispass.2005.1430554openalex-snapshot
BioBench: A Benchmark Suite of Bioinformatics Applications
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1996.566457openalex-snapshot
Assigning confidence to conditional branch predictions
inferredcites →https://doi.org/10.1109/micro.1998.742769openalex-snapshot
Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes
inferredcites →https://doi.org/10.1109/micro.2005.13openalex-snapshot
Automatic Thread Extraction with Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/micro.2005.38openalex-snapshot
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution
inferredcites →https://doi.org/10.1109/micro.2006.20openalex-snapshot
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
inferredcites →https://doi.org/10.1109/mm.2011.2openalex-snapshot
Bobcat: AMD's Low-Power x86 Processor
inferredcites →https://doi.org/10.1109/pact.1998.727261openalex-snapshot
Dynamic hammock predication for non-predicated instruction set architectures
inferredcites →https://doi.org/10.1109/pact.2007.4336199openalex-snapshot
Speculative Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/pact.2007.66openalex-snapshot
Speculative Decoupled Software Pipelining
inferredcites →https://doi.org/10.1145/1024393.1024407openalex-snapshot
Continual flow pipelines
inferredcites →https://doi.org/10.1145/1064978.1065034openalex-snapshot
Pin
inferredcites →https://doi.org/10.1145/1065010.1065034openalex-snapshot
Pin
inferredcites →https://doi.org/10.1145/1067649.801719openalex-snapshot
Decoupled access/execute computer architectures
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/165939.165952openalex-snapshot
The effectiveness of decoupling
inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot
McPAT
inferredcites →https://doi.org/10.1145/1772954.1772973openalex-snapshot
Decoupled software pipelining creates parallelization opportunities
inferredcites →https://doi.org/10.1145/2155620.2155635openalex-snapshot
A new case for the TAGE branch predictor
inferredcites →https://doi.org/10.1145/300979.300995openalex-snapshot
Simultaneous subordinate microthreading (SSMT)
inferredcites →https://doi.org/10.1145/379240.379246openalex-snapshot
Execution-based prediction using speculative slices
inferredcites →https://doi.org/10.1145/545214.545250openalex-snapshot
Difficult-path branch prediction using subordinate microthreads
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1147/rd.516.0639openalex-snapshot
IBM POWER6 microarchitecture
inferredcites →https://doi.org/10.5555/243846.243880openalex-snapshot
Assigning confidence to conditional branch predictions
inferredcites →https://doi.org/10.5555/243846.243881openalex-snapshot
Compiler synthesized dynamic branch prediction
inferredcites →https://doi.org/10.5555/290940.290960openalex-snapshot
Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes
inferredcites →https://doi.org/10.5555/522344.825698openalex-snapshot
Dynamic hammock predication for non-predicated instruction set architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071026openalex-snapshot
Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00019openalex-snapshot
Auto-Predication of Critical Branches
inferred← citeshttps://doi.org/10.1109/lca.2020.2978841openalex-snapshot
Post-Silicon Microarchitecture
inferred← citeshttps://doi.org/10.1109/micro.2018.00018openalex-snapshot
Architectural Support for Probabilistic Branches
inferred← citeshttps://doi.org/10.1109/tc.2014.2361526openalex-snapshot
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching
inferred← citeshttps://doi.org/10.1109/uksim.2014.35openalex-snapshot
Optimal Pipeline Performance via Transactional Slice with No Branch Prediction Overhead
inferred← citeshttps://doi.org/10.1109/uksim.2017.15openalex-snapshot
Analysis of Performance of Instruction Pipeline with Transactional Slice Mechanism in CMP
inferred← citeshttps://doi.org/10.1145/2749469.2750400openalex-snapshot
Branch vanguard
inferred← citeshttps://doi.org/10.1145/2872887.2750400openalex-snapshot
Branch vanguard
inferred← citeshttps://doi.org/10.1145/3243176.3243185openalex-snapshot
Cimple: instruction and memory level parallelism
inferred← citeshttps://doi.org/10.1145/3410463.3414628openalex-snapshot
Opportunistic Early Pipeline Re-steering for Data-dependent Branches
inferred← citeshttps://doi.org/10.1145/3452099openalex-snapshot
Fast Key-Value Lookups with Node Tracker
inferred← citeshttps://doi.org/10.11591/telkomnika.v11i11.3216openalex-snapshot
Instruction Pipeline Efficient Mechanism with maximum hit ratio
inferred← citeshttps://doi.org/10.23860/thesis-constant-matthew-2020openalex-snapshot
ANALYZING THE PERFORMANCE IMPACT OF PARALLEL LATENCY IN THE PIPELINE
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