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AMD Fusion APU: Llano
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.8147openalex-snapshot
Evaluating the potential of disaggregated memory systems for HPC applications
inferred← citeshttps://doi.org/10.1007/978-1-4614-3296-8_11openalex-snapshot
CPU-GPU System Designs for High Performance Cloud Computing
inferred← citeshttps://doi.org/10.1007/978-3-319-09967-5_16openalex-snapshot
Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors
inferred← citeshttps://doi.org/10.1007/978-3-319-26928-3_9openalex-snapshot
On a Dynamic Scheduling Approach to Execute OpenCL Jobs on APUs
inferred← citeshttps://doi.org/10.1007/978-3-319-62932-2_5openalex-snapshot
Performance Evaluation of Two Load Balancing Algorithms on a Hybrid Parallel Architecture
inferred← citeshttps://doi.org/10.1007/978-3-319-78054-2_16openalex-snapshot
Dynamic Load Balancing Algorithm for Heterogeneous Clusters
inferred← citeshttps://doi.org/10.1007/978-3-642-55224-3_57openalex-snapshot
Efficient Execution of Erasure Codes on AMD APU Architecture
inferred← citeshttps://doi.org/10.1007/978-981-10-6388-6_26openalex-snapshot
A Novel Statistical Power Model for Integrated GPU with Optimization
inferred← citeshttps://doi.org/10.1007/s00500-017-2786-1openalex-snapshot
A statistic approach for power analysis of integrated GPU
inferred← citeshttps://doi.org/10.1007/s10586-017-1295-4openalex-snapshot
PRODA: improving parallel programs on GPUs through dependency analysis
inferred← citeshttps://doi.org/10.1007/s10766-018-0617-3openalex-snapshot
ASW: Accelerating Smith–Waterman Algorithm on Coupled CPU–GPU Architecture
inferred← citeshttps://doi.org/10.1007/s11227-018-2525-0openalex-snapshot
An adaptive breadth-first search algorithm on integrated architectures
inferred← citeshttps://doi.org/10.1007/s11390-015-1510-9openalex-snapshot
Cooperative Computing Techniques for a Deeply Fused and Heterogeneous Many-Core Processor Architecture
inferred← citeshttps://doi.org/10.1007/s11554-012-0272-7openalex-snapshot
Performance analysis of a novel GPU computation-to-core mapping scheme for robust facet image modeling
inferred← citeshttps://doi.org/10.1007/s42514-019-00008-6openalex-snapshot
Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors
inferred← citeshttps://doi.org/10.1016/j.amc.2015.03.072openalex-snapshot
On the use of multiple heterogeneous devices to speedup the execution of a computational model of the Human Immune System
inferred← citeshttps://doi.org/10.1016/j.future.2014.12.014openalex-snapshot
A scalable thread scheduling co-processor based on data-flow principles
inferred← citeshttps://doi.org/10.1016/j.future.2017.02.012openalex-snapshot
Accurately modeling the on-chip and off-chip GPU memory subsystem
inferred← citeshttps://doi.org/10.1016/j.jcss.2014.06.017openalex-snapshot
MCMG simulator: A unified simulation framework for CPU and graphic GPU
inferred← citeshttps://doi.org/10.1016/j.jpdc.2015.06.010openalex-snapshot
A framework for general sparse matrix–matrix multiplication on GPUs and heterogeneous processors
inferred← citeshttps://doi.org/10.1016/j.jss.2016.02.009openalex-snapshot
GPU-SAM: Leveraging multi-GPU split-and-merge execution for system-wide real-time support
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.06.007openalex-snapshot
Improved GPU SIMD control flow efficiency via hybrid warp size mechanism
inferred← citeshttps://doi.org/10.1016/j.parco.2015.04.004openalex-snapshot
Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors
inferred← citeshttps://doi.org/10.1016/j.suscom.2013.11.001openalex-snapshot
A survey of architectural techniques for improving cache power efficiency
inferred← citeshttps://doi.org/10.1109/access.2019.2910932openalex-snapshot
Towards Energy-Efficient Heterogeneous Multicore Architectures for Edge Computing
inferred← citeshttps://doi.org/10.1109/access.2020.2986335openalex-snapshot
Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip
inferred← citeshttps://doi.org/10.1109/acsd.2014.28openalex-snapshot
Studying the Interplay of Concurrency, Performance, Energy and Reliability with ArchOn -- An Architecture-Open Resource-Driven Cross-Layer Modelling Framework
inferred← citeshttps://doi.org/10.1109/aspdac.2015.7059106openalex-snapshot
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies
inferred← citeshttps://doi.org/10.1109/cases.2013.6662513openalex-snapshot
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
inferred← citeshttps://doi.org/10.1109/cicc.2014.6946043openalex-snapshot
AMD SOC power management: Improving performance/watt using run-time feedback
inferred← citeshttps://doi.org/10.1109/cluster.2013.6702667openalex-snapshot
Highly optimized full GPU-acceleration of non-hydrostatic weather model SCALE-LES
inferred← citeshttps://doi.org/10.1109/etfa.2013.6648166openalex-snapshot
GPGPU for industrial control systems
inferred← citeshttps://doi.org/10.1109/globecom38437.2019.9013267openalex-snapshot
VirtualStack: Green High Performance Network Protocol Processing Leveraging FPGAs
inferred← citeshttps://doi.org/10.1109/hipc.2016.027openalex-snapshot
Telescoping Architectures: Evaluating Next-Generation Heterogeneous Computing
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835930openalex-snapshot
QuickRelease: A throughput-oriented approach to release consistency on GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056041openalex-snapshot
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408580openalex-snapshot
AccelFlow: Orchestrating an On-Package Ensemble of Fine-Grained Accelerators for Microservices
inferred← citeshttps://doi.org/10.1109/i2ct42659.2018.9058254openalex-snapshot
General purpose Arithmetic computation on AMD Platform, APU Based with Integrated GPU and finding Empirical results of GPGPU Acceleration
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378642openalex-snapshot
Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures
inferred← citeshttps://doi.org/10.1109/icces.2016.7821983openalex-snapshot
Accelerated Processing Unit (APU) potential: N-body simulation case study
inferred← citeshttps://doi.org/10.1109/icpp.2014.42openalex-snapshot
Hydra: Efficient Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architecture
inferred← citeshttps://doi.org/10.1109/icpp.2015.64openalex-snapshot
Green-CM: Energy Efficient Contention Management for Transactional Memory
inferred← citeshttps://doi.org/10.1109/igcc.2016.7892617openalex-snapshot
An energy-efficient bandwidth allocation method for single-chip heterogeneous processor
inferred← citeshttps://doi.org/10.1109/iiswc55918.2022.00013openalex-snapshot
UVM Discard: Eliminating Redundant Memory Transfers for Accelerators
inferred← citeshttps://doi.org/10.1109/ipdps.2017.124openalex-snapshot
Co-Run Scheduling with Power Cap on Integrated CPU-GPU Systems
inferred← citeshttps://doi.org/10.1109/isca.2014.6853197openalex-snapshot
An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs
inferred← citeshttps://doi.org/10.1109/isca.2014.6853208openalex-snapshot
Enabling preemptive multiprogramming on GPUs
inferred← citeshttps://doi.org/10.1109/isicir.2016.7829731openalex-snapshot
An implementation of analytical power model on integrated GPU
inferred← citeshttps://doi.org/10.1109/ispass.2016.7482092openalex-snapshot
GSI: A GPU Stall Inspector to characterize the sources of memory stalls for tightly coupled GPUs
inferred← citeshttps://doi.org/10.1109/ispdc.2017.16openalex-snapshot
Understanding the Impact of Fine-Grained Data Sharing and Thread Communication on Heterogeneous Workload Development
inferred← citeshttps://doi.org/10.1109/iwem.2019.8887952openalex-snapshot
Research on the Influence of CPU Power Management on the Performance of Parallel FDTD
inferred← citeshttps://doi.org/10.1109/jetcas.2011.2158343openalex-snapshot
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/lascas51355.2021.9459181openalex-snapshot
EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors
inferred← citeshttps://doi.org/10.1109/mdat.2013.2274651openalex-snapshot
Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs
inferred← citeshttps://doi.org/10.1109/mm.2014.3openalex-snapshot
Kabini: An AMD Accelerated Processing Unit System on A Chip
inferred← citeshttps://doi.org/10.1109/pdcat.2012.34openalex-snapshot
Accelerating High Performance Computing Applications: Using CPUs, GPUs, Hybrid CPU/GPU, and FPGAs
inferred← citeshttps://doi.org/10.1109/resdis56595.2022.00006openalex-snapshot
Methodology for Evaluating the Potential of Disaggregated Memory Systems
inferred← citeshttps://doi.org/10.1109/rtsi.2015.7325080openalex-snapshot
Reconfigurable antenna system for wireless applications
inferred← citeshttps://doi.org/10.1109/sc.2016.74openalex-snapshot
Elastic Multi-resource Fairness: Balancing Fairness and Efficiency in Coupled CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/tc.2012.286openalex-snapshot
Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking
inferred← citeshttps://doi.org/10.1109/tc.2015.2512860openalex-snapshot
Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/tkde.2020.2975652openalex-snapshot
A Survey on Spark Ecosystem: Big Data Processing Infrastructure, Machine Learning, and Applications
inferred← citeshttps://doi.org/10.1109/tmc.2021.3139940openalex-snapshot
MVPose: Realtime Multi-Person Pose Estimation Using Motion Vector on Mobile Devices
inferred← citeshttps://doi.org/10.1109/tpds.2015.2453965openalex-snapshot
Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2759219openalex-snapshot
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2019.8920389openalex-snapshot
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications
inferred← citeshttps://doi.org/10.1145/2370816.2370873openalex-snapshot
Workload and power budget partitioning for single-chip heterogeneous processors
inferred← citeshttps://doi.org/10.1145/2576779.2576790openalex-snapshot
Power Modeling for Heterogeneous Processors
inferred← citeshttps://doi.org/10.1145/2588768.2576790openalex-snapshot
Power Modeling for Heterogeneous Processors
inferred← citeshttps://doi.org/10.1145/2628071.2628096openalex-snapshot
Memory scheduling towards high-throughput cooperative heterogeneous computing
inferred← citeshttps://doi.org/10.1145/2659000openalex-snapshot
A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window Applications
inferred← citeshttps://doi.org/10.1145/2678373.2665702openalex-snapshot
Enabling preemptive multiprogramming on GPUs
inferred← citeshttps://doi.org/10.1145/2678373.2665709openalex-snapshot
An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs
inferred← citeshttps://doi.org/10.1145/2742854.2742862openalex-snapshot
Fast packet forwarding engine based on software circuits
inferred← citeshttps://doi.org/10.1145/2788396openalex-snapshot
A Survey of CPU-GPU Heterogeneous Computing Techniques
inferred← citeshttps://doi.org/10.1145/2925426.2926265openalex-snapshot
Scheduling Tasks with Mixed Timing Constraints in GPU-Powered Real-Time Systems
inferred← citeshttps://doi.org/10.1145/3123939.3136952openalex-snapshot
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs
inferred← citeshttps://doi.org/10.1145/3243176.3243210openalex-snapshot
On-the-fly workload partitioning for integrated CPU/GPU architectures
inferred← citeshttps://doi.org/10.1145/3330152openalex-snapshot
Thread Batching for High-performance Energy-efficient GPU Memory Design
inferred← citeshttps://doi.org/10.1145/3422575.3422792openalex-snapshot
X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures
inferred← citeshttps://doi.org/10.1145/3485126openalex-snapshot
Query Processing on Heterogeneous CPU/GPU Systems
inferred← citeshttps://doi.org/10.1145/3526241.3530316openalex-snapshot
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference
inferred← citeshttps://doi.org/10.13140/rg.2.1.1237.0806openalex-snapshot
Optimization of Data-Parallel Scientific Applications on Highly Heterogeneous Modern HPC Platforms
inferred← citeshttps://doi.org/10.14288/1.0167209openalex-snapshot
Accelerating irregular applications on parallel hybrid platforms
inferred← citeshttps://doi.org/10.1587/transele.e96.c.528openalex-snapshot
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM
inferred← citeshttps://doi.org/10.18419/opus-3054openalex-snapshot
Framework für beschleunigte Monte-Carlo-Molekularsimulationen auf hybriden Architekturen
inferred← citeshttps://doi.org/10.23919/date.2019.8715078openalex-snapshot
Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters
inferred← citeshttps://doi.org/10.3390/electronics9111825openalex-snapshot
Resource-Aware Device Allocation of Data-Parallel Applications on Heterogeneous Systems
inferred← citeshttps://doi.org/10.4018/978-1-5225-0287-6.ch006openalex-snapshot
Multicore and Manycore
inferred← citeshttps://doi.org/10.4995/thesis/10251/125477openalex-snapshot
Efficient L2 Cache Management to Boost GPGPU Performance
inferred← citeshttps://doi.org/10.5555/3014904.3015005openalex-snapshot
Elastic multi-resource fairness: balancing fairness and efficiency in coupled CPU-GPU architectures
inferred← citeshttps://doi.org/10.5753/wscad.2020.14057openalex-snapshot
PampaFreq: Otimizando o EDP de Aplicações Paralelas em Processadores AMD
inferred← citeshttps://doi.org/10.70675/cf508f02z8d3dz419ezaf16z55d93104a2e6openalex-snapshot
Transformer le TLP en DLP avec l'architecture de vectorisation dynamique inter-thread
inferred← citeshttps://doi.org/10.70675/eec34495zfc63z42eez866bz6197e4eb5edbopenalex-snapshot
Large-scale network simulation over heterogeneous computing architecture
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