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Task Migration in Mesh NoCs over Virtual Point-to-Point Connections
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.ins.2006.02.007openalex-snapshot
Task migration in all-port wormhole-routed 2D mesh multicomputers
inferredcites →https://doi.org/10.1016/j.parco.2008.03.009openalex-snapshot
Design and performance evaluation of combined first-fit task allocation and migration strategies in mesh multiprocessor systems
inferredcites →https://doi.org/10.1016/s0020-0190(00)00005-3openalex-snapshot
Task migration in 2D wormhole-routed mesh multicomputers
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/aspdac.2010.5419827openalex-snapshot
A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip
inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/date.2005.201openalex-snapshot
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC
inferredcites →https://doi.org/10.1109/date.2005.91openalex-snapshot
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles
inferredcites →https://doi.org/10.1109/date.2006.243952openalex-snapshot
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study
inferredcites →https://doi.org/10.1109/ipdps.2009.5161128openalex-snapshot
A multi-objective strategy for concurrent mapping and routing in networks on chip
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isvlsi.2007.32openalex-snapshot
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1109/tcad.2010.2048402openalex-snapshot
Virtual Point-to-Point Connections for NoCs
inferredcites →https://doi.org/10.1109/vlsisoc.2007.4402516openalex-snapshot
Impact of task migration in NoC-based MPSoCs for soft real-time applications
inferredcites →https://doi.org/10.1145/1127908.1127997openalex-snapshot
Selective code/data migration for reducing communication energy in embedded MpSoC architectures
inferredcites →https://doi.org/10.1145/1150343.1150359openalex-snapshot
Dynamic task binding for hardware/software reconfigurable networks
inferredcites →https://doi.org/10.1145/1255456.1255460openalex-snapshot
On-chip communication architecture exploration
inferredcites →https://doi.org/10.1145/1403375.1403709openalex-snapshot
Dynamic task allocation strategies in MPSoC for soft real-time applications
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-014-1144-7openalex-snapshot
A task migration mechanism for distributed many-core operating systems
inferred← citeshttps://doi.org/10.1007/s11227-014-1240-8openalex-snapshot
Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.012openalex-snapshot
Multiobjectivism in Dark Silicon Age
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.11.004openalex-snapshot
Packet triggered prediction based task migration for network-on-chip
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.05.014openalex-snapshot
CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era
inferred← citeshttps://doi.org/10.1016/j.sysarc.2013.03.011openalex-snapshot
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs
inferred← citeshttps://doi.org/10.1049/iet-cdt.2015.0131openalex-snapshot
Performance/energy aware task migration algorithm for many‐core chips
inferred← citeshttps://doi.org/10.1109/fccm.2012.30openalex-snapshot
Remote Execution in Distributed Memory MPSoC
inferred← citeshttps://doi.org/10.1109/iccca.2012.6179171openalex-snapshot
Multiple task migration in mesh network on chips over virtual point-to-point connections
inferred← citeshttps://doi.org/10.1109/iscas.2012.6272114openalex-snapshot
Proposal and evaluation of a task migration protocol for NoC-based MPSoCs
inferred← citeshttps://doi.org/10.1109/isvlsi.2013.6654651openalex-snapshot
Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes
inferred← citeshttps://doi.org/10.1109/pdcat.2011.2openalex-snapshot
A Distributed Task Migration Scheme for Mesh-Based Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/pdp.2012.37openalex-snapshot
Packet Triggered Prediction Based Task Migration for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/pdp.2016.88openalex-snapshot
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks
inferred← citeshttps://doi.org/10.1109/socc.2016.7905455openalex-snapshot
SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC
inferred← citeshttps://doi.org/10.5120/ijca2015904575openalex-snapshot
Performance Improvement in Multiprocessors using Two Row Boundary Allocation Method and Online Dynamic Compaction Algorithm
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