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METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01088834openalex-snapshot
Pipelined processors and worst case execution times
inferredcites →https://doi.org/10.1016/b978-155860702-6/50016-8openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.1109/12.743411openalex-snapshot
Bounding pipeline and instruction cache performance
inferredcites →https://doi.org/10.1109/icdcs.1996.507899openalex-snapshot
Synchronization protocols in distributed real-time systems
inferredcites →https://doi.org/10.1109/mm.2004.1289290openalex-snapshot
IBM power5 chip: a dual-core multithreaded processor
inferredcites →https://doi.org/10.1109/mm.2004.37openalex-snapshot
QoS for high-performance SMT processors in embedded systems
inferredcites →https://doi.org/10.1109/real.1994.342718openalex-snapshot
Bounding worst-case instruction cache performance
inferredcites →https://doi.org/10.1109/real.1994.342726openalex-snapshot
An accurate worst case timing analysis technique for RISC processors
inferredcites →https://doi.org/10.1109/real.1999.818824openalex-snapshot
Timing anomalies in dynamically scheduled microprocessors
inferredcites →https://doi.org/10.1109/real.2002.1181569openalex-snapshot
Soft real-time scheduling on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1109/real.2004.24openalex-snapshot
Hard Real-Time Communication in Bus-Based Networks
inferredcites →https://doi.org/10.1109/rttas.2000.852468openalex-snapshot
Bandwidth guarantee in a distributed multimedia file system using network attached autonomous disks
inferredcites →https://doi.org/10.1109/rttas.2004.1317261openalex-snapshot
Storage access support for soft real-time applications
inferredcites →https://doi.org/10.1109/tpds.2002.1158264openalex-snapshot
Mediaworm: a qos capable router architecture for clusters
inferredcites →https://doi.org/10.1145/1023833.1023837openalex-snapshot
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
inferredcites →https://doi.org/10.1145/232973.232996openalex-snapshot
Rotating combined queueing (RCQ)
inferredcites →https://doi.org/10.1145/321738.321743openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.1145/354880.354905openalex-snapshot
A dynamic memory management unit for embedded real-time system-on-a-chip
inferredcites →https://doi.org/10.1145/502217.502240openalex-snapshot
Efficient longest executable path search for programs with complex flows and pipeline effects
inferredcites →https://doi.org/10.1145/859618.859659openalex-snapshot
Virtual simple architecture (VISA)
inferredcites →https://doi.org/10.1145/859658.859659openalex-snapshot
Virtual simple architecture (VISA)
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Intelligent Dynamic Instruction Scheduling: An AI-Driven Approach for Next-Generation Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-21878-1_74openalex-snapshot
Minimizing Technical Complexities in Emerging Cloud Computing Platforms
inferred← citeshttps://doi.org/10.1007/s11042-011-0782-5openalex-snapshot
Resource optimization in distributed real-time multimedia applications
inferred← citeshttps://doi.org/10.1007/s11241-012-9160-2openalex-snapshot
Timing analysis of concurrent programs running on shared cache multi-cores
inferred← citeshttps://doi.org/10.1007/s11761-011-0089-4openalex-snapshot
Virtualised e-Learning on the IRMOS real-time Cloud
inferred← citeshttps://doi.org/10.1016/j.future.2012.05.009openalex-snapshot
Dynamic, behavioral-based estimation of resource provisioning based on high-level application terms in Cloud platforms
inferred← citeshttps://doi.org/10.1016/j.jpdc.2012.01.013openalex-snapshot
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
inferred← citeshttps://doi.org/10.1109/date.2011.5763145openalex-snapshot
Architectures and modeling of predictable memory controllers for improved system integration
inferred← citeshttps://doi.org/10.1109/dsd.2009.167openalex-snapshot
Composable Resource Sharing Based on Latency-Rate Servers
inferred← citeshttps://doi.org/10.1109/hpcc.2014.60openalex-snapshot
Performance Implication of Multicore Cache Locking on General-Purpose Processors
inferred← citeshttps://doi.org/10.1109/isca.2008.31openalex-snapshot
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
inferred← citeshttps://doi.org/10.1109/iscc.2011.5984009openalex-snapshot
Translation of application-level terms to resource-level attributes across the Cloud stack layers
inferred← citeshttps://doi.org/10.1109/isorc.2011.36openalex-snapshot
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks
inferred← citeshttps://doi.org/10.1109/micro.2007.17openalex-snapshot
A Framework for Providing Quality of Service in Chip Multi-Processors
inferred← citeshttps://doi.org/10.1109/rtas.2011.34openalex-snapshot
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtcsa.2010.35openalex-snapshot
Classification and Analysis of Predictable Memory Patterns
inferred← citeshttps://doi.org/10.1109/rtcsa.2014.6910550openalex-snapshot
A mixed critical memory controller using bank privatization and fixed priority scheduling
inferred← citeshttps://doi.org/10.1109/rtss.2009.32openalex-snapshot
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
inferred← citeshttps://doi.org/10.1109/soca.2010.5707166openalex-snapshot
Virtualised e-Learning with real-time guarantees on the IRMOS platform
inferred← citeshttps://doi.org/10.1145/1394608.1382130openalex-snapshot
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
inferred← citeshttps://doi.org/10.1145/1543753.1543755openalex-snapshot
Service level agreement for multithreaded processors
inferred← citeshttps://doi.org/10.1145/1811212.1811220openalex-snapshot
Modeling shared cache and bus in multi-cores for timing analysis
inferred← citeshttps://doi.org/10.1145/1880037.1880039openalex-snapshot
Quality of service shared cache management in chip multiprocessor architecture
inferred← citeshttps://doi.org/10.1145/2452537.2452538openalex-snapshot
Architectural time-predictability factor (ATF)
inferred← citeshttps://doi.org/10.1145/2544350.2544353openalex-snapshot
Virtual execution platforms for mixed-time-criticality systems
inferred← citeshttps://doi.org/10.4018/978-1-4666-0879-5.ch8.7openalex-snapshot
Service Level Agreements for Real-Time Service-Oriented Infrastructures
inferred← citeshttps://doi.org/10.4018/978-1-4666-0879-5.ch807openalex-snapshot
Service Level Agreements for Real-Time Service-Oriented Infrastructures
inferred← citeshttps://doi.org/10.4018/978-1-4666-0906-8.ch006openalex-snapshot
A Study on the Effect of Application and Resource Characteristics on the QoS in Service Provisioning Environments
inferred← citeshttps://doi.org/10.4018/978-1-60960-827-9.ch008openalex-snapshot
Service Level Agreements for Real-Time Service-Oriented Infrastructures
inferred← citeshttps://doi.org/10.4018/jdst.2010090804openalex-snapshot
A Study on the Effect of Application and Resource Characteristics on the QoS in Service Provisioning Environments
inferred← citeshttps://doi.org/10.5220/0004851505430550openalex-snapshot
Challenges of Capacity Modelling in Complex IT Architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93335openalex-snapshot
Improving cache Behavior in CMP architectures throug cache partitioning techniques
inferred← citeshttps://doi.org/10.6100/ir658012openalex-snapshot
Predictable and composable system-on-chip memory controllers
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