On the public citation graph
A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems
0 signed · 73 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/date.2009.5090695openalex-snapshot
A file-system-aware FTL design for flash-memory storage systems
inferredcites →https://doi.org/10.1109/date.2009.5090717openalex-snapshot
KAST: K-associative sector translation for NAND flash memory in real-time systems
inferredcites →https://doi.org/10.1109/rttas.2002.1137393openalex-snapshot
An adaptive striping architecture for flash memory storage systems of embedded systems
inferredcites →https://doi.org/10.1109/sasp.2008.4570788openalex-snapshot
Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems
inferredcites →https://doi.org/10.1109/tce.2002.1010143openalex-snapshot
A space-efficient flash translation layer for CompactFlash systems
inferredcites →https://doi.org/10.1145/1289816.1289878openalex-snapshot
Performance improvement of block based NAND flash translation layer
inferredcites →https://doi.org/10.1145/1379272openalex-snapshot
Proceedings of the 2nd international workshop on Scalable stream processing system
inferredcites →https://doi.org/10.1145/1450135.1450140openalex-snapshot
A time-predictable system initialization design for huge-capacity flash-memory storage systems
inferredcites →https://doi.org/10.1145/1629911.1630130openalex-snapshot
A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems
inferredcites →https://doi.org/10.1145/1878961.1878991openalex-snapshot
Demand-based block-level address mapping in large-scale NAND flash storage systems
inferredcites →https://doi.org/10.5555/1874620.1874715openalex-snapshot
A file-system-aware FTL design for flash-memory storage systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-33201-7_6openalex-snapshot
NVRAM-Assisted Optimization Techniques for Flash Memory Management in Embedded Sensor Nodes
inferred← citeshttps://doi.org/10.1007/978-3-319-68542-7_49openalex-snapshot
Workload-Aware Page-Level Flash Translation Layer for NAND Flash-Based Storage Systems
inferred← citeshttps://doi.org/10.1007/s10617-014-9144-7openalex-snapshot
Loop transformations for flash memory: cost models and performance effects
inferred← citeshttps://doi.org/10.1007/s10617-014-9154-5openalex-snapshot
Data-assemblage: a translation-page-aware data block allocation strategy for flash-based solid state drives
inferred← citeshttps://doi.org/10.1016/j.future.2024.107483openalex-snapshot
Program context-assisted address translation for high-capacity SSDs
inferred← citeshttps://doi.org/10.1016/j.ijleo.2015.06.065openalex-snapshot
A data-driven superblock-based flash translation layer
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.02.008openalex-snapshot
Virtual duplication and mapping prefetching for emerging storage primitives in NAND flash memory storage systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2014.01.002openalex-snapshot
Memory efficient and scalable address mapping for flash storage devices
inferred← citeshttps://doi.org/10.1016/j.sysarc.2018.05.006openalex-snapshot
A reliability enhanced video storage architecture in hybrid SLC/MLC NAND flash memory
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.02.007openalex-snapshot
Reinforcement learning-driven address mapping and caching for flash-based remote sensing image processing
inferred← citeshttps://doi.org/10.1016/j.sysarc.2020.101810openalex-snapshot
PHDFS: Optimizing I/O performance of HDFS in deep learning cloud computing platform
inferred← citeshttps://doi.org/10.1109/access.2021.3138832openalex-snapshot
IBU: An In-Block Update Address Mapping Scheme for Solid-State Drives
inferred← citeshttps://doi.org/10.1109/aspdac.2013.6509616openalex-snapshot
Optimizing translation information management in NAND flash memory storage systems
inferred← citeshttps://doi.org/10.1109/dac.2018.8465808openalex-snapshot
FMMU: A Hardware-Accelerated Flash Map Management Unit for Scalable Performance of Flash-Based SSDs
inferred← citeshttps://doi.org/10.1109/date.2012.6176443openalex-snapshot
Dual Greedy: Adaptive garbage collection for page-mapping solid-state disks
inferred← citeshttps://doi.org/10.1109/hpcc-css-icess.2015.272openalex-snapshot
Optimizing Emerging Storage Primitives with Virtualization for Flash Memory Storage Systems
inferred← citeshttps://doi.org/10.1109/hpcc.2014.57openalex-snapshot
SRFTL: An Adaptive Superblock-Based Real-Time Flash Translation Layer for NAND Flash Memory
inferred← citeshttps://doi.org/10.1109/icassp.2018.8462147openalex-snapshot
A Reliable Video Storage Architecture in Hybrid SLC/MLC Nand Flash
inferred← citeshttps://doi.org/10.1109/icsec.2014.6978234openalex-snapshot
SCFTL: An efficient caching strategy for page-level flash translation layer
inferred← citeshttps://doi.org/10.1109/jproc.2017.2679490openalex-snapshot
Software Support Inside and Outside Solid-State Devices for High Performance and High Efficiency
inferred← citeshttps://doi.org/10.1109/nas.2017.8026838openalex-snapshot
A Hash-Based Space-Efficient Page-Level FTL for Large-Capacity SSDs
inferred← citeshttps://doi.org/10.1109/nvmsa.2015.7304366openalex-snapshot
Logical data packing for multi-chip flash-memory storage systems
inferred← citeshttps://doi.org/10.1109/nvmsa.2018.00018openalex-snapshot
F2FS Aware Mapping Cache Design on Solid State Drives
inferred← citeshttps://doi.org/10.1109/pdgc.2016.7913185openalex-snapshot
A study on performance evaluation of conventional cache replacement algorithms: A review
inferred← citeshttps://doi.org/10.1109/rtas.2012.27openalex-snapshot
Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems
inferred← citeshttps://doi.org/10.1109/rtas.2015.7108392openalex-snapshot
Optimizing deterministic garbage collection in NAND flash storage systems
inferred← citeshttps://doi.org/10.1109/rtcsa52859.2021.00029openalex-snapshot
An FTL-Aware Host System Alleviating Severe Long Latency of NAND Flash-based Storage
inferred← citeshttps://doi.org/10.1109/rtss.2011.40openalex-snapshot
PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2014.2329680openalex-snapshot
On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems
inferred← citeshttps://doi.org/10.1109/tc.2015.2485221openalex-snapshot
TreeFTL: An Efficient Workload-Adaptive Algorithm for RAM Buffer Management of NAND Flash-Based Devices
inferred← citeshttps://doi.org/10.1109/tc.2019.2962691openalex-snapshot
A Modeling Framework for Reliability of Erasure Codes in SSD Arrays
inferred← citeshttps://doi.org/10.1109/tc.2021.3116862openalex-snapshot
Enabling the Duo-phase Data Management to Realize Longevity Bit-alterable Flash Memory
inferred← citeshttps://doi.org/10.1109/tcad.2017.2729405openalex-snapshot
An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache
inferred← citeshttps://doi.org/10.1109/tce.2014.7027338openalex-snapshot
Map cache management using dual granularity for mobile storage systems
inferred← citeshttps://doi.org/10.1109/tce.2020.2991213openalex-snapshot
GFTL: Group-Level Mapping in Flash Translation Layer to Provide Efficient Address Translation for NAND Flash-Based SSDs
inferred← citeshttps://doi.org/10.1109/tcsi.2018.2851141openalex-snapshot
Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD
inferred← citeshttps://doi.org/10.1109/tii.2019.2932115openalex-snapshot
DPAM: A Demand-Based Page-Level Address Mappings Algorithm in Flash Memory for Smart Industrial Edge Devices
inferred← citeshttps://doi.org/10.1109/tmc.2018.2869737openalex-snapshot
File Fragmentation in Mobile Devices: Measurement, Evaluation, and Treatment
inferred← citeshttps://doi.org/10.1109/tpds.2013.205openalex-snapshot
Design and Implementation of Holistic Scheduling and Efficient Storage for FlexRay
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2294462openalex-snapshot
A Unified Write Buffer Cache Management Scheme for Flash Memory
inferred← citeshttps://doi.org/10.1145/2554850.2554939openalex-snapshot
Optimizing FTL mapping cache for random-write workloads using adaptive block partitioning
inferred← citeshttps://doi.org/10.1145/2741948.2741949openalex-snapshot
An efficient page-level FTL to optimize address translation in flash memory
inferred← citeshttps://doi.org/10.1145/2947658openalex-snapshot
An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems
inferred← citeshttps://doi.org/10.1145/2968478.2968503openalex-snapshot
I/O scheduling with mapping cache awareness for flash based storage systems
inferred← citeshttps://doi.org/10.1145/3051123openalex-snapshot
Understanding and Alleviating the Impact of the Flash Address Translation on Solid State Devices
inferred← citeshttps://doi.org/10.1145/3366715.3366746openalex-snapshot
Improving Flash Translation Layer Performance by Using Log Block Mapping Scheme and Two-level Buffer for Address Translation Information
inferred← citeshttps://doi.org/10.1145/3767335openalex-snapshot
HyTorC: Hybrid Address Translation for SSDs Supporting Compression
inferred← citeshttps://doi.org/10.1145/3799988openalex-snapshot
Seg-FTL: A new Segment-Based FTL with Dynamic Linear Model for Enhanced SSD Performance
inferred← citeshttps://doi.org/10.1155/2022/3376904openalex-snapshot
URM: A Unified RAM Management Scheme for NAND Flash Storage Devices
inferred← citeshttps://doi.org/10.13328/j.cnki.jos.004528openalex-snapshot
Optimized Address Translation Method for Flash Memory
inferred← citeshttps://doi.org/10.1504/ijes.2014.063814openalex-snapshot
A real-time flash translation layer via adaptive partial garbage collection
inferred← citeshttps://doi.org/10.1587/elex.12.20150211openalex-snapshot
3DFTL: a three-level demand-based translation strategy for flash device
inferred← citeshttps://doi.org/10.1587/elex.16.20190521openalex-snapshot
An implementation of low latency address-mapping logic for SSD controllers
inferred← citeshttps://doi.org/10.48550/arxiv.1704.03168openalex-snapshot
FMMU: A Hardware-Automated Flash Map Management Unit for Scalable Performance of NAND Flash-Based SSDs
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.