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Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.689649openalex-snapshot
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
inferredcites →https://doi.org/10.1109/aspdac.2006.1594787openalex-snapshot
Analysis of scratch-pad and data-cache performance using statistical methods
inferredcites →https://doi.org/10.1109/codes.2002.1003604openalex-snapshot
Scratchpad memory: a design alternative for cache on-chip memory in embedded systems
inferredcites →https://doi.org/10.1109/date.2002.998306openalex-snapshot
Assigning program and data objects to scratchpad for energy reduction
inferredcites →https://doi.org/10.1109/date.2004.1269069openalex-snapshot
Cache-aware scratchpad allocation algorithm
inferredcites →https://doi.org/10.1109/date.2005.97openalex-snapshot
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access
inferredcites →https://doi.org/10.1109/date.2007.364510openalex-snapshot
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
inferredcites →https://doi.org/10.1109/ecrts.2007.37openalex-snapshot
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
inferredcites →https://doi.org/10.1109/ecrts.2009.21openalex-snapshot
A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay
inferredcites →https://doi.org/10.1109/edtc.1997.582323openalex-snapshot
Efficient utilization of scratch-pad memory in embedded processor applications
inferredcites →https://doi.org/10.1109/real.1989.63574openalex-snapshot
SMART (strategic memory allocation for real-time) cache design
inferredcites →https://doi.org/10.1109/real.1990.128764openalex-snapshot
SMART (strategic memory allocation for real-time) cache design using the MIPS R3000
inferredcites →https://doi.org/10.1109/real.2002.1181567openalex-snapshot
Low-complexity algorithms for static cache locking in multitasking hard real-time systems
inferredcites →https://doi.org/10.1109/rtas.2005.12openalex-snapshot
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
inferredcites →https://doi.org/10.1109/rtas.2006.14openalex-snapshot
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
inferredcites →https://doi.org/10.1109/rtas.2007.23openalex-snapshot
Optimal Unified Data Allocation and Task Scheduling for Real-Time Multi-Tasking Systems
inferredcites →https://doi.org/10.1109/rtas.2010.36openalex-snapshot
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
inferredcites →https://doi.org/10.1109/rtss.2005.45openalex-snapshot
WCET Centric Data Allocation to Scratchpad Memory
inferredcites →https://doi.org/10.1109/sips.2004.1363044openalex-snapshot
Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems
inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1145/1118299.1118486openalex-snapshot
Analysis of scratch-pad and data-cache performance using statistical methods
inferredcites →https://doi.org/10.1145/216633.216677openalex-snapshot
Compiler support for software-based cache partitioning
inferredcites →https://doi.org/10.1145/502217.502223openalex-snapshot
Heterogeneous memory management for embedded systems
inferredcites →https://doi.org/10.1145/502218.502223openalex-snapshot
Heterogeneous memory management for embedded systems
inferredcites →https://doi.org/10.1145/944645.944698openalex-snapshot
Accurate estimation of cache-related preemption delay
inferredcites →https://doi.org/10.1145/944696.944698openalex-snapshot
Accurate estimation of cache-related preemption delay
inferredcites →https://doi.org/10.5555/787260.787762openalex-snapshot
Efficient utilization of scratch-pad memory in embedded processor applications
inferredcites →https://doi.org/10.5555/882452.874376openalex-snapshot
Assigning Program and Data Objects to Scratchpad for Energy Reduction
inferredcites →https://doi.org/10.5555/968879.969148openalex-snapshot
Cache-aware scratchpad allocation algorithm
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-94-017-7267-9_27openalex-snapshot
Memory-Aware Optimization of Embedded Software for Multiple Objectives
inferred← citeshttps://doi.org/10.1007/978-94-017-7358-4_27-2openalex-snapshot
Memory-Aware Optimization of Embedded Software for Multiple Objectives
inferred← citeshttps://doi.org/10.1007/s11042-018-6783-xopenalex-snapshot
A spill data aware memory assignment technique for improving power consumption of multimedia memory systems
inferred← citeshttps://doi.org/10.1109/asap.2013.6567593openalex-snapshot
Hybrid SPM-cache architectures to achieve high time predictability and performance
inferred← citeshttps://doi.org/10.1109/aspdac.2015.7059043openalex-snapshot
Managing hybrid on-chip scratchpad and cache memories for multi-tasking embedded systems
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys60770.2023.00017openalex-snapshot
ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators
inferred← citeshttps://doi.org/10.1109/hpcc.2014.100openalex-snapshot
Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches
inferred← citeshttps://doi.org/10.1109/hpcc.2014.59openalex-snapshot
Exploiting Hybrid SPM-Cache Architectures to Reduce Energy Consumption for Embedded Computing
inferred← citeshttps://doi.org/10.1109/hpcc.and.euc.2013.60openalex-snapshot
Data Allocation for Embedded Systems with Hybrid On-Chip Scratchpad and Caches
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357185openalex-snapshot
Hybrid scratchpad and cache memory management for energy-efficient parallel HEVC encoding
inferred← citeshttps://doi.org/10.1109/isorc.2014.59openalex-snapshot
A Real-Time Instruction Cache with High Average-Case Performance
inferred← citeshttps://doi.org/10.1109/isorc.2015.11openalex-snapshot
Hardware-Based Performance Enhancement Guaranteed Caches
inferred← citeshttps://doi.org/10.1109/isqed.2015.7085411openalex-snapshot
Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures
inferred← citeshttps://doi.org/10.1109/pccc.2013.6742770openalex-snapshot
Reducing worst-case execution time of hybrid SPM-caches
inferred← citeshttps://doi.org/10.1109/rtss.2013.42openalex-snapshot
Task Set Synthesis with Cost Minimization for Sporadic Real-Time Tasks
inferred← citeshttps://doi.org/10.1109/tpds.2013.2297308openalex-snapshot
Real-Time Task Scheduling on Island-Based Multi-Core Platforms
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2544811openalex-snapshot
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
inferred← citeshttps://doi.org/10.1142/s0218126618500809openalex-snapshot
Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches
inferred← citeshttps://doi.org/10.1145/2656106.2656124openalex-snapshot
Reducing cache leakage energy for hybrid SPM-cache architectures
inferred← citeshttps://doi.org/10.1145/3721288openalex-snapshot
PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures
inferred← citeshttps://doi.org/10.21742/ijsh.2019.13.2.02openalex-snapshot
Low-End Memory Subsystem Optimization Process
inferred← citeshttps://doi.org/10.31142/ijtsrd14351openalex-snapshot
A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction
inferred← citeshttps://doi.org/10.31142/ijtsrd14354openalex-snapshot
A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction
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