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Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-44520-x_26openalex-snapshot
A Fast and Accurate Approach to Analyze Cache Memory Behavior
inferredcites →https://doi.org/10.1023/a:1008190423977openalex-snapshot
Timing Analysis for Data and Wrap-Around Fill Caches
inferredcites →https://doi.org/10.1023/a:1011132221066openalex-snapshot
A Comparison of Static Analysis and Evolutionary Testing for the Verification of Timing Constraints
inferredcites →https://doi.org/10.1049/sej.1993.0034openalex-snapshot
Applying new scheduling theory to static priority pre-emptive scheduling
inferredcites →https://doi.org/10.1109/12.689649openalex-snapshot
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
inferredcites →https://doi.org/10.1109/32.392980openalex-snapshot
An accurate worst case timing analysis for RISC processors
inferredcites →https://doi.org/10.1109/32.950317openalex-snapshot
Bounding cache-related preemption delay for real-time systems
inferredcites →https://doi.org/10.1109/ecrts.2005.26openalex-snapshot
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
inferredcites →https://doi.org/10.1109/emwrts.1996.557940openalex-snapshot
Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems
inferredcites →https://doi.org/10.1109/hpca.2002.995708openalex-snapshot
Let's study whole-program cache behaviour analytically
inferredcites →https://doi.org/10.1109/pact.1999.807544openalex-snapshot
Automatic analytical modeling for the estimation of cache misses
inferredcites →https://doi.org/10.1109/real.1989.63567openalex-snapshot
The rate monotonic scheduling algorithm: exact characterization and average case behavior
inferredcites →https://doi.org/10.1109/real.1996.563722openalex-snapshot
Cache modeling for real-time software: beyond direct mapped instruction caches
inferredcites →https://doi.org/10.1109/real.2002.1181567openalex-snapshot
Low-complexity algorithms for static cache locking in multitasking hard real-time systems
inferredcites →https://doi.org/10.1109/rtas.2005.12openalex-snapshot
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
inferredcites →https://doi.org/10.1109/rttas.1996.509540openalex-snapshot
Efficient worst case timing analysis of data caching
inferredcites →https://doi.org/10.1145/1017753.1017798openalex-snapshot
Multiple process execution in cache related preemption delay analysis
inferredcites →https://doi.org/10.1145/325478.325479openalex-snapshot
Cache miss equations
inferredcites →https://doi.org/10.1145/334012.334025openalex-snapshot
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
inferredcites →https://doi.org/10.1145/378795.378859openalex-snapshot
Exact analysis of the cache behavior of nested loops
inferredcites →https://doi.org/10.1145/781027.781062openalex-snapshot
Data cache locking for higher program predictability
inferredcites →https://doi.org/10.1145/885651.781062openalex-snapshot
Data cache locking for higher program predictability
inferredcites →https://doi.org/10.1145/944645.944698openalex-snapshot
Accurate estimation of cache-related preemption delay
inferredcites →https://doi.org/10.1145/944696.944698openalex-snapshot
Accurate estimation of cache-related preemption delay

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Making DRAM refresh predictable
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Cache-related preemption delay via useful cache blocks: Survey and redefinition
inferred← citeshttps://doi.org/10.1109/date.2012.6176520openalex-snapshot
Preemption delay analysis for floating non-preemptive region scheduling
inferred← citeshttps://doi.org/10.1109/ecrts.2008.29openalex-snapshot
Bounding Shared-Stack Usage in Systems with Offsets and Precedences
inferred← citeshttps://doi.org/10.1109/ecrts.2009.21openalex-snapshot
A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay
inferred← citeshttps://doi.org/10.1109/ecrts.2010.21openalex-snapshot
Investigating Average versus Worst-Case Timing Behavior of Data Caches and Data Scratchpads
inferred← citeshttps://doi.org/10.1109/ecrts.2010.23openalex-snapshot
Making DRAM Refresh Predictable
inferred← citeshttps://doi.org/10.1109/ecrts.2010.9openalex-snapshot
Preemption Points Placement for Sporadic Task Sets
inferred← citeshttps://doi.org/10.1109/ecrts.2013.26openalex-snapshot
Outstanding Paper Award: Making Shared Caches More Predictable on Multicore Platforms
inferred← citeshttps://doi.org/10.1109/ecrts.2015.22openalex-snapshot
Minimizing Cache Overhead via Loaded Cache Blocks and Preemption Placement
inferred← citeshttps://doi.org/10.1109/etfa.2014.7005198openalex-snapshot
Temporal isolation with preemption delay accounting
inferred← citeshttps://doi.org/10.1109/euc.2011.46openalex-snapshot
Job Phasing Aware Preemption Deferral
inferred← citeshttps://doi.org/10.1109/rtas.2008.18openalex-snapshot
Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions
inferred← citeshttps://doi.org/10.1109/rtas.2009.23openalex-snapshot
Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information
inferred← citeshttps://doi.org/10.1109/rtas.2009.28openalex-snapshot
Bounding Worst-Case Response Times of Tasks under PIP
inferred← citeshttps://doi.org/10.1109/rtas.2010.14openalex-snapshot
Response Time versus Utilization in Scheduler Overhead Accounting
inferred← citeshttps://doi.org/10.1109/rtas.2010.21openalex-snapshot
Studying the Applicability of the Scratchpad Memory Management Unit
inferred← citeshttps://doi.org/10.1109/rtas.2011.33openalex-snapshot
A Predictable Execution Model for COTS-Based Embedded Systems
inferred← citeshttps://doi.org/10.1109/rtas.2012.19openalex-snapshot
Explicit Reservation of Local Memory in a Predictable, Preemptive Multitasking Real-Time System
inferred← citeshttps://doi.org/10.1109/rtas.2012.22openalex-snapshot
Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation
inferred← citeshttps://doi.org/10.1109/rtas.2015.7108391openalex-snapshot
Providing task isolation via TLB coloring
inferred← citeshttps://doi.org/10.1109/rtas.2017.35openalex-snapshot
Scope-Aware Useful Cache Block Analysis for Data Cache Related Preemption Delay
inferred← citeshttps://doi.org/10.1109/rtcsa.2008.42openalex-snapshot
Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/rtcsa50079.2020.9203646openalex-snapshot
Integrating Preemption Thresholds with Limited Preemption Scheduling
inferred← citeshttps://doi.org/10.1109/rtss.2006.18openalex-snapshot
Determining Maximum Stack Usage in Preemptive Shared Stack Systems
inferred← citeshttps://doi.org/10.1109/rtss.2006.49openalex-snapshot
Tightening the Bounds on Feasible Preemption Points
inferred← citeshttps://doi.org/10.1109/rtss.2007.13openalex-snapshot
Distributed Minimal Time Convergecast Scheduling for Small or Sparse Data Sources
inferred← citeshttps://doi.org/10.1109/rtss.2007.15openalex-snapshot
Toward the Predictable Integration of Real-Time COTS Based Systems
inferred← citeshttps://doi.org/10.1109/rtss.2007.24openalex-snapshot
Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
inferred← citeshttps://doi.org/10.1109/rtss.2007.51openalex-snapshot
Static Scheduling and Software Synthesis for Dataflow Graphs with Symbolic Model-Checking
inferred← citeshttps://doi.org/10.1109/rtss.2008.42openalex-snapshot
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
inferred← citeshttps://doi.org/10.1109/rtss.2009.48openalex-snapshot
Rapid Early-Phase Virtual Integration
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Optimizing Tunable WCET with Shared Resource Allocation and Arbitration in Hard Real-Time Multicore Systems
inferred← citeshttps://doi.org/10.1109/sies.2012.6356570openalex-snapshot
An improved preemption delay upper bound for floating non-preemptive region
inferred← citeshttps://doi.org/10.1109/tc.2009.156openalex-snapshot
Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems
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Time-Predictable Out-of-Order Execution for Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1109/tcad.2019.2937807openalex-snapshot
Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2158249openalex-snapshot
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors
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Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
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Parametric timing analysis and its application to dynamic voltage scaling
inferred← citeshttps://doi.org/10.1145/1880050.1880063openalex-snapshot
Tightening the bounds on feasible preemptions
inferred← citeshttps://doi.org/10.1145/2355585.2355593openalex-snapshot
Static analysis of the worst-case memory performance for irregular codes with indirections
inferred← citeshttps://doi.org/10.1145/2523070openalex-snapshot
Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system
inferred← citeshttps://doi.org/10.1145/2968478.2968481openalex-snapshot
Cache-related preemption delay analysis for multi-level inclusive caches
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A First Step Toward Using Quantum Computing for Low-level WCETs Estimations
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