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Optimizing Tunable WCET with Shared Resource Allocation and Arbitration in Hard Real-Time Multicore Systems
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/b978-155860702-6/50016-8openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.1109/les.2010.2041634openalex-snapshot
An Analyzable Memory Controller for Hard Real-Time CMPs
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/rtas.2006.14openalex-snapshot
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
inferredcites →https://doi.org/10.1109/rtas.2008.6openalex-snapshot
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
inferredcites →https://doi.org/10.1109/rtas.2010.24openalex-snapshot
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
inferredcites →https://doi.org/10.1109/rtas.2011.35openalex-snapshot
Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip
inferredcites →https://doi.org/10.1109/rtcsa.2008.42openalex-snapshot
Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems
inferredcites →https://doi.org/10.1109/rtss.2007.13openalex-snapshot
Distributed Minimal Time Convergecast Scheduling for Small or Sparse Data Sources
inferredcites →https://doi.org/10.1109/rtss.2007.24openalex-snapshot
Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
inferredcites →https://doi.org/10.1109/rtss.2009.32openalex-snapshot
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
inferredcites →https://doi.org/10.1109/vlsi.2008.33openalex-snapshot
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
inferredcites →https://doi.org/10.1145/1176760.1176809openalex-snapshot
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
inferredcites →https://doi.org/10.1145/1391469.1391545openalex-snapshot
Exploring locking & partitioning for predictable shared caches on multi-cores
inferredcites →https://doi.org/10.1145/1450095.1450117openalex-snapshot
Predictable programming on a precision timed architecture
inferredcites →https://doi.org/10.1145/1555754.1555764openalex-snapshot
Hardware support for WCET analysis of hard real-time multicore systems
inferredcites →https://doi.org/10.1145/1646353.1646371openalex-snapshot
Managing contention for shared resources on multicore processors
inferredcites →https://doi.org/10.1145/1669112.1669176openalex-snapshot
Optimizing shared cache behavior of chip multiprocessors
inferredcites →https://doi.org/10.1145/1735970.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferredcites →https://doi.org/10.1145/1736020.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferredcites →https://doi.org/10.1145/1811212.1811220openalex-snapshot
Modeling shared cache and bus in multi-cores for timing analysis
inferredcites →https://doi.org/10.1145/321738.321743openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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SecureCore: A multicore-based intrusion detection architecture for real-time embedded systems
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Trading Cores for Memory Bandwidth in Real-Time Systems
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The Split-Phase Synchronisation Technique: Reducing the Pessimism in the WCET Analysis of Parallelised Hard Real-Time Programs
inferred← citeshttps://doi.org/10.1109/rtss.2018.00059openalex-snapshot
Shedding the Shackles of Time-Division Multiplexing
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CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems
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inferred← citeshttps://doi.org/10.1109/samos.2014.6893196openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/sies.2013.6601468openalex-snapshot
Deconstructing bus access control policies for Real-Time multicores
inferred← citeshttps://doi.org/10.1109/wcsp.2015.7341307openalex-snapshot
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A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems
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DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance
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Proceedings of the International Conference on Embedded Software
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Work-in-Progress: Flexible bus arbitration in mixed criticality systems
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Duetto: Latency Guarantees at Minimal Performance Cost
inferred← citeshttps://doi.org/10.4230/oasics.wcet.2014.31openalex-snapshot
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art
inferred← citeshttps://doi.org/10.5821/dissertation-2117-125025openalex-snapshot
Enhancing timing analysis for COTS multicores for safety-related industry : a software approach
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Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
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Modular Avionics Software Integration on Multi-Core COTS : certification-Compliant Methodology and Timing Analysis Metrics for Legacy Software Reuse in Modern Aerospace Systems
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Response time analysis of parameterized dataflow applications on heterogeneous SW/HW systems
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Work-conserving dynamic TDM-based memory arbitration for multi-criticality real-time systems
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