On the public citation graph

Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling

https://doi.org/10.1109/rtss.2015.13

0 signed · 41 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s11241-011-9129-6openalex-snapshot

Making DRAM refresh predictable

inferredcites →https://doi.org/10.1109/cse.2013.106openalex-snapshot

Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses

inferredcites →https://doi.org/10.1109/ecrts.2014.37openalex-snapshot

A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems

inferredcites →https://doi.org/10.1109/les.2010.2041634openalex-snapshot

An Analyzable Memory Controller for Hard Real-Time CMPs

inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot

Bounding memory interference delay in COTS-based multi-core systems

inferredcites →https://doi.org/10.1109/rtas.2014.6925999openalex-snapshot

PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms

inferredcites →https://doi.org/10.1109/rtss.2013.44openalex-snapshot

Worst Case Analysis of DRAM Latency in Multi-requestor Systems

inferredcites →https://doi.org/10.1109/rtss.2014.23openalex-snapshot

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study

inferredcites →https://doi.org/10.1109/tcad.2009.2013287openalex-snapshot

Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems

inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot

MiBench: A free, commercially representative embedded benchmark suite

inferredcites →https://doi.org/10.1109/wwc.2001.990739openalex-snapshot

MiBench: A free, commercially representative embedded benchmark suite

inferredcites →https://doi.org/10.1145/1289816.1289877openalex-snapshot

Predator

inferredcites →https://doi.org/10.1145/2039370.2039388openalex-snapshot

PRET DRAM controller

inferredcites →https://doi.org/10.1145/2370816.2370869openalex-snapshot

A software memory partition approach for eliminating bank-level interference in multicore systems

inferredcites →https://doi.org/10.1145/2435227.2435260openalex-snapshot

Timing effects of DDR memory systems in hard real-time multicore architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11241-016-9253-4openalex-snapshot

A composable worst case latency analysis for multi-rank DRAM devices under open row policy

inferred← citeshttps://doi.org/10.1007/s11241-019-09338-8openalex-snapshot

Reduced latency DRAM for multi-core safety-critical real-time systems

inferred← citeshttps://doi.org/10.1007/s11241-023-09411-3openalex-snapshot

A formal framework to design and prove trustworthy memory controllers

inferred← citeshttps://doi.org/10.1016/j.jpdc.2020.01.001openalex-snapshot

PMSMC: Priority-based Multi-requestor Scheduler for Embedded System Memory Controller

inferred← citeshttps://doi.org/10.1109/access.2022.3151891openalex-snapshot

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

inferred← citeshttps://doi.org/10.1109/access.2025.3645136openalex-snapshot

Reassessing March Test Effectiveness in System Memory Error Detection Through Inductive Fault Analysis

inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00047openalex-snapshot

Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study

inferred← citeshttps://doi.org/10.1109/ecrts.2016.8openalex-snapshot

Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance

inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643473openalex-snapshot

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

inferred← citeshttps://doi.org/10.1109/nkcon56289.2022.10126989openalex-snapshot

Implementation of Manifold Harassers to Aggravate Memory Failure Rate During Post-silicon Validation

inferred← citeshttps://doi.org/10.1109/rtas.2017.12openalex-snapshot

A Requests Bundling DRAM Controller for Mixed-Criticality Systems

inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00-15openalex-snapshot

DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining

inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00011openalex-snapshot

BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors

inferred← citeshttps://doi.org/10.1109/rtas68450.2026.00025openalex-snapshot

Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time Systems

inferred← citeshttps://doi.org/10.1109/rtss.2018.00062openalex-snapshot

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

inferred← citeshttps://doi.org/10.1109/rtss59052.2023.00031openalex-snapshot

Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems

inferred← citeshttps://doi.org/10.1109/tc.2017.2714672openalex-snapshot

Tackling the Bus Turnaround Overhead in Real-Time SDRAM Controllers

inferred← citeshttps://doi.org/10.1109/ted.2023.3326798openalex-snapshot

Modeling the Thermal Characteristics of Stacked 2T0C Memory Array Based on InGaZnO 4 Thin-Film Transistors

inferred← citeshttps://doi.org/10.1109/tetc.2025.3645133openalex-snapshot

Exploring Time Predictability for High-Bandwidth Memory Technology

inferred← citeshttps://doi.org/10.1145/3158208openalex-snapshot

A Comparative Study of Predictable DRAM Controllers

inferred← citeshttps://doi.org/10.1145/3534879.3534907openalex-snapshot

A Coq Framework for More Trustworthy DRAM Controllers

inferred← citeshttps://doi.org/10.23919/date.2017.7927063openalex-snapshot

Architecting high-speed command schedulers for open-row real-time SDRAM controllers

inferred← citeshttps://doi.org/10.3390/mi16040409openalex-snapshot

ADPO: Adaptive DRAM Controller for Performance Optimization

inferred← citeshttps://doi.org/10.6100/ir850540openalex-snapshot

Design and formal analysis of real-time memory controllers

inferred← citeshttps://doi.org/10.70675/5a9cee0bz162ez41ebz9f00z288fb5fd7460openalex-snapshot

CoqDRAM - A Foundation for Designing Formally Proven Memory Controllers

inferred← citeshttps://doi.org/10.70675/977a83d4z9a75z4155z9917zfb2237dfcb7copenalex-snapshot

Predictable execution on many-core processors

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.