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A Comparative Study of Predictable DRAM Controllers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4419-8207-0openalex-snapshot
Memory Controllers for Real-Time Embedded Systems
inferredcites →https://doi.org/10.1109/acssc.2010.5757922openalex-snapshot
A PRET architecture supporting concurrent programs with composable timing properties
inferredcites →https://doi.org/10.1109/compsac.2014.54openalex-snapshot
Integrated Modular Avionics (IMA) Partition Scheduling with Conflict-Free I/O for Multicore Avionics Systems
inferredcites →https://doi.org/10.1109/cpsna.2015.24openalex-snapshot
MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems
inferredcites →https://doi.org/10.1109/ecrts.2014.18openalex-snapshot
Dynamic Command Scheduling for Real-Time Memory Controllers
inferredcites →https://doi.org/10.1109/ecrts.2014.37openalex-snapshot
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
inferredcites →https://doi.org/10.1109/ecrts.2015.24openalex-snapshot
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems
inferredcites →https://doi.org/10.1109/ecrts.2016.8openalex-snapshot
Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/lca.2015.2414456openalex-snapshot
Ramulator: A Fast and Extensible DRAM Simulator
inferredcites →https://doi.org/10.1109/les.2010.2041634openalex-snapshot
An Analyzable Memory Controller for Hard Real-Time CMPs
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/mm.2009.74openalex-snapshot
A Benchmark Characterization of the EEMBC Benchmark Suite
inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot
Bounding memory interference delay in COTS-based multi-core systems
inferredcites →https://doi.org/10.1109/rtas.2015.7108454openalex-snapshot
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
inferredcites →https://doi.org/10.1109/rtas.2015.7108455openalex-snapshot
A predictable and command-level priority-based DRAM controller for mixed-criticality systems
inferredcites →https://doi.org/10.1109/rtas.2016.7461341openalex-snapshot
Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers
inferredcites →https://doi.org/10.1109/rtcsa.2014.6910550openalex-snapshot
A mixed critical memory controller using bank privatization and fixed priority scheduling
inferredcites →https://doi.org/10.1109/rtss.2013.44openalex-snapshot
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
inferredcites →https://doi.org/10.1109/rtss.2014.23openalex-snapshot
A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study
inferredcites →https://doi.org/10.1109/rtss.2015.13openalex-snapshot
Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling
inferredcites →https://doi.org/10.1109/tcad.2009.2013287openalex-snapshot
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
inferredcites →https://doi.org/10.1109/tpds.2016.2526003openalex-snapshot
BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling
inferredcites →https://doi.org/10.1109/tse.1997.637142openalex-snapshot
Real-time Systems Symposium (RTSS'96)
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.5555/2485288.2485418openalex-snapshot
Conservative open-page policy for mixed time-criticality memory controllers
inferredcites →https://doi.org/10.7873/date.2013openalex-snapshot
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11241-019-09338-8openalex-snapshot
Reduced latency DRAM for multi-core safety-critical real-time systems
inferred← citeshttps://doi.org/10.1007/s11241-023-09411-3openalex-snapshot
A formal framework to design and prove trustworthy memory controllers
inferred← citeshttps://doi.org/10.1016/j.cor.2022.105774openalex-snapshot
A MILP approach to DRAM access worst-case analysis
inferred← citeshttps://doi.org/10.1016/j.jpdc.2020.01.001openalex-snapshot
PMSMC: Priority-based Multi-requestor Scheduler for Embedded System Memory Controller
inferred← citeshttps://doi.org/10.1016/j.mejo.2026.107410openalex-snapshot
A synthesizable bandwidth monitoring module for DDR4 memory controllers: RTL design and post-implementation analysis
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103068openalex-snapshot
Time-predictable task-to-thread mapping in multi-core processors
inferred← citeshttps://doi.org/10.1088/1742-6596/2414/1/012003openalex-snapshot
Research the SDRAM Controller Based on FPGA
inferred← citeshttps://doi.org/10.1109/access.2022.3151891openalex-snapshot
A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643473openalex-snapshot
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/icm48031.2019.9021469openalex-snapshot
Managing DRAM Interference in Mixed Criticality Embedded Systems
inferred← citeshttps://doi.org/10.1109/lca.2020.3008288openalex-snapshot
MCsim: An Extensible DRAM Memory Controller Simulator
inferred← citeshttps://doi.org/10.1109/rtas.2017.12openalex-snapshot
A Requests Bundling DRAM Controller for Mixed-Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00-15openalex-snapshot
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
inferred← citeshttps://doi.org/10.1109/rtas65571.2025.00019openalex-snapshot
Consistency-Aware and Predictable Memory Processing for Safety-Critical Out-of-Order Multicores
inferred← citeshttps://doi.org/10.1109/rtas68450.2026.00025openalex-snapshot
Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtss.2018.00062openalex-snapshot
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?
inferred← citeshttps://doi.org/10.1109/rtss46320.2019.00045openalex-snapshot
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtss49844.2020.00029openalex-snapshot
The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications
inferred← citeshttps://doi.org/10.1109/rtss66672.2025.00056openalex-snapshot
Work-in-Progress: A First Practical Look at Arm's MPAM for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/tc.2022.3193624openalex-snapshot
DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2022.3202720openalex-snapshot
Analyzing Arm's MPAM From the Perspective of Time Predictability
inferred← citeshttps://doi.org/10.1109/tcad.2018.2857379openalex-snapshot
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012210openalex-snapshot
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms
inferred← citeshttps://doi.org/10.1145/3274281openalex-snapshot
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis
inferred← citeshttps://doi.org/10.1145/3323212openalex-snapshot
A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems
inferred← citeshttps://doi.org/10.1145/3453417.3453426openalex-snapshot
Heterogeneous multicore SDRAM interference analysis
inferred← citeshttps://doi.org/10.1145/3489467openalex-snapshot
Holistic Resource Allocation Under Federated Scheduling for Parallel Real-time Tasks
inferred← citeshttps://doi.org/10.1145/3556975openalex-snapshot
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems
inferred← citeshttps://doi.org/10.1145/3676536.3676807openalex-snapshot
A Framework for Explainable, Comprehensive, and Customizable Memory-Centric Workloads
inferred← citeshttps://doi.org/10.70675/5a9cee0bz162ez41ebz9f00z288fb5fd7460openalex-snapshot
CoqDRAM - A Foundation for Designing Formally Proven Memory Controllers
inferred← citeshttps://doi.org/10.70675/70cf5f84z93f1z489bzbdf0ze19a1fa1854fopenalex-snapshot
Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA Computing Platforms
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