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Reconciling the Tension Between Hardware Isolation and Data Sharing in Mixed-Criticality, Multicore Systems

https://doi.org/10.1109/rtss.2016.015

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Mixed-Criticality Real-Time Scheduling for Multicore Systems

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Worst case delay analysis for memory interference in multicore systems

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CAMA: A Predictable Cache-Aware Memory Allocator

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Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

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A Coordinated Approach for Practical OS-Level Cache Management in Multi-core Real-Time Systems

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OUTSTANDING PAPER: Evaluation of Cache Partitioning for Hard Real-Time Systems

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Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform

inferredcites →https://doi.org/10.1109/emsoft.2013.6658595openalex-snapshot

Scheduling of mixed-criticality applications on resource-sharing multicore systems

inferredcites →https://doi.org/10.1109/ipdps.2015.120openalex-snapshot

Recovering from Overload in Multicore Mixed-Criticality Systems

inferredcites →https://doi.org/10.1109/rtas.2012.24openalex-snapshot

RTOS Support for Multicore Mixed-Criticality Systems

inferredcites →https://doi.org/10.1109/rtas.2013.6531078openalex-snapshot

Real-time cache management framework for multi-core architectures

inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot

Bounding memory interference delay in COTS-based multi-core systems

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PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms

inferredcites →https://doi.org/10.1109/rtas.2015.7108452openalex-snapshot

Memory efficient global scheduling of real-time tasks

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A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems

inferredcites →https://doi.org/10.1109/rtas.2015.7108455openalex-snapshot

A predictable and command-level priority-based DRAM controller for mixed-criticality systems

inferredcites →https://doi.org/10.1109/rtas.2016.7461322openalex-snapshot

Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation

inferredcites →https://doi.org/10.1109/rtas.2016.7461323openalex-snapshot

Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning

inferredcites →https://doi.org/10.1109/rtas.2016.7461327openalex-snapshot

Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems

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Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems

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Trading Cores for Memory Bandwidth in Real-Time Systems

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Supporting Graph-Based Real-Time Applications in Distributed Systems

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Minimizing response times of automotive dataflows on multicore

inferredcites →https://doi.org/10.1109/rtss.2007.47openalex-snapshot

Preemptive Scheduling of Multi-criticality Systems with Varying Degrees of Execution Time Assurance

inferredcites →https://doi.org/10.1109/rtss.2010.38openalex-snapshot

Supporting Soft Real-Time DAG-Based Systems on Multiprocessors with No Utilization Loss

inferredcites →https://doi.org/10.1109/rtss.2014.23openalex-snapshot

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study

inferredcites →https://doi.org/10.1109/rtss.2015.36openalex-snapshot

Cache Sharing and Isolation Tradeoffs in Multicore Mixed-Criticality Systems

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Inter-Core Communication Mechanisms for Microkernel Operating System based on Signal Transmission and Shared Memory

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DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems

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Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform

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Mixed Criticality on Multi-cores Accounting for Resource Stress and Resource Sensitivity

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High Performance and Predictable Shared Last-level Cache for Safety-Critical Systems

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Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems

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Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems

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