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An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.orgel.2009.07.005openalex-snapshot
Charge trapping in organic transistor memories: On the role of electrons and holes
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Carbon Nanotube Synaptic Transistor Network for Pattern Recognition
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Gradient-based learning applied to document recognition
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Analog in-memory subthreshold deep neural network accelerator
inferredcites →https://doi.org/10.1109/cvpr.2014.81openalex-snapshot
Rich Feature Hierarchies for Accurate Object Detection and Semantic Segmentation
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Going deeper with convolutions
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Deep Residual Learning for Image Recognition
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A 9b 2GS/s 45mW 2X-interleaved ADC
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PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
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Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2−x/Pt Memristors
inferredcites →https://doi.org/10.1109/irps.2015.7112816openalex-snapshot
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
inferredcites →https://doi.org/10.1109/iscas.2012.6271561openalex-snapshot
Memristive computing- multiplication and correlation
inferredcites →https://doi.org/10.1109/isscc.2014.6757323openalex-snapshot
1.1 Computing's energy problem (and what we can do about it)
inferredcites →https://doi.org/10.1109/isscc.2016.7418007openalex-snapshot
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
inferredcites →https://doi.org/10.1109/isscc.2017.7870349openalex-snapshot
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems
inferredcites →https://doi.org/10.1109/jproc.2003.811702openalex-snapshot
Introduction to flash memory
inferredcites →https://doi.org/10.1109/jproc.2017.2761740openalex-snapshot
Efficient Processing of Deep Neural Networks: A Tutorial and Survey
inferredcites →https://doi.org/10.1109/led.2015.2504952openalex-snapshot
The Impact of Self-Heating on Charge Trapping in High- $k$ -Metal-Gate nFETs
inferredcites →https://doi.org/10.1109/led.2016.2633490openalex-snapshot
Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies
inferredcites →https://doi.org/10.1109/led.2017.2723319openalex-snapshot
Unsupervised Learning Using Charge-Trap Transistors
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A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
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Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element
inferredcites →https://doi.org/10.1109/tnn.2002.1000139openalex-snapshot
Competitive learning with floating-gate circuits
inferredcites →https://doi.org/10.1109/vlsic.2014.6858453openalex-snapshot
An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS
inferredcites →https://doi.org/10.1109/vlsic.2016.7573462openalex-snapshot
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
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Neuromorphic computing gets ready for the (really) big time
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A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing
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ImageNet classification with deep convolutional neural networks
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In-Datacenter Performance Analysis of a Tensor Processing Unit
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Very Deep Convolutional Networks for Large-Scale Image Recognition
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Memristor based computation-in-memory architecture for data-intensive applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Memristor‐Based Neuromorphic Chips
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A Power-Efficient Analog Circuit for Winner-Take-All and Loser-Take-All Implementation for Edge Detection Applications
inferred← citeshttps://doi.org/10.1007/s10470-020-01713-xopenalex-snapshot
Design and validation of an artificial neural network based on analog circuits
inferred← citeshttps://doi.org/10.1007/s10470-020-01733-7openalex-snapshot
Optimization techniques for analog and RF circuit designs: an overview
inferred← citeshttps://doi.org/10.1007/s10470-025-02486-xopenalex-snapshot
Exploring analog VLSI architectures for linear regulators and high-speed receivers: a comprehensive SLR and emerging innovations
inferred← citeshttps://doi.org/10.1007/s41939-024-00517-0openalex-snapshot
In-memory computing: characteristics, spintronics, and neural network applications insights
inferred← citeshttps://doi.org/10.1016/b978-0-12-820758-1.00002-9openalex-snapshot
The evolving role of storage-class memory in servers and large systems
inferred← citeshttps://doi.org/10.1016/j.jcis.2026.139943openalex-snapshot
Interface-engineered Gd₂O₃/ZrO₂ bilayer memristor for emulating synaptic plasticity in neuromorphic systems
inferred← citeshttps://doi.org/10.1016/j.sse.2023.108783openalex-snapshot
Evidence of Transport Degradation in 22 nm FD-SOI Charge Trapping Transistors for Neural Network Applications
inferred← citeshttps://doi.org/10.1038/s41467-022-29171-1openalex-snapshot
Programmable black phosphorus image sensor for broadband optoelectronic edge computing
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Memtransistor for bio-inspired neuromorphic computing: A perspective from device physics to neural and sensory systems
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Ferroelectric HfO 2 -based synaptic devices: recent trends and prospects
inferred← citeshttps://doi.org/10.1098/rsta.2019.0166openalex-snapshot
Neural network design for energy-autonomous artificial intelligence applications using temporal encoding
inferred← citeshttps://doi.org/10.1109/icnwc68145.2026.11518041openalex-snapshot
Transistor-level Implementation of Artificial Analog Neural Network: VGA-based Multipliers and CMOS Transimpedance Sigmoid Activation
inferred← citeshttps://doi.org/10.1109/icrc60800.2023.10386858openalex-snapshot
Thermodynamic AI and the Fluctuation Frontier
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10182219openalex-snapshot
Characterization of Charge-Trap-Transistor (CTT) Threshold Voltage Degradation and Differential-Pair-Based Memory Design
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558145openalex-snapshot
A Charge-Trap-Transistor-Based Fully Analog Machine Learning Inference Engine for Audio Keyword Spotting
inferred← citeshttps://doi.org/10.1109/isocc53507.2021.9613930openalex-snapshot
CTT-based Non-Volatile Deep Neural Network Accelerator Design
inferred← citeshttps://doi.org/10.1109/isqed65160.2025.11014347openalex-snapshot
Behavioral Model of Charge-Trap Transistors for Neuromorphic Systems
inferred← citeshttps://doi.org/10.1109/jeds.2020.2993859openalex-snapshot
Impact of the Crystal Phase of ZrO₂ on Charge Trapping Memtransistor as Synaptic Device for Neural Network Application
inferred← citeshttps://doi.org/10.1109/jeds.2020.3025336openalex-snapshot
Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks
inferred← citeshttps://doi.org/10.1109/jetcas.2023.3244775openalex-snapshot
CTT-Based Scalable Neuromorphic Architecture
inferred← citeshttps://doi.org/10.1109/jmw.2024.3504332openalex-snapshot
Microwave Pioneers: Mau-Chung Frank Chang, “The Power of Connections”
inferred← citeshttps://doi.org/10.1109/jxcdc.2021.3098469openalex-snapshot
Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications
inferred← citeshttps://doi.org/10.1109/mwscas.2019.8885281openalex-snapshot
CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections
inferred← citeshttps://doi.org/10.1109/mwscas53549.2025.11244495openalex-snapshot
Reconfigurable Analog Neural Networks: Architecture, Design, and Performance Evaluation
inferred← citeshttps://doi.org/10.1109/ojcas.2023.3332853openalex-snapshot
A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm
inferred← citeshttps://doi.org/10.1109/tasc.2021.3135264openalex-snapshot
Boltzmann Machine Using Superconducting Circuits
inferred← citeshttps://doi.org/10.1109/tcsi.2021.3134313openalex-snapshot
An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory
inferred← citeshttps://doi.org/10.1109/ted.2019.2933484openalex-snapshot
Charge-Trap Transistors for CMOS-Only Analog Memory
inferred← citeshttps://doi.org/10.1109/ted.2020.3008887openalex-snapshot
Neuro-Inspired-in-Memory Computing Using Charge-Trapping MemTransistor on Germanium as Synaptic Device
inferred← citeshttps://doi.org/10.1109/ted.2024.3418726openalex-snapshot
Unraveling the Dynamics of HfO2-Based NW-CTT as an Artificial Synapse
inferred← citeshttps://doi.org/10.1109/ted.2025.3540764openalex-snapshot
Impact of Gate/Drain Biases in FDSOI-Based Analog Synapse on Artificial Neural-Network Performance
inferred← citeshttps://doi.org/10.1109/tnet.2022.3225883openalex-snapshot
AirNN: Over-the-Air Computation for Neural Networks via Reconfigurable Intelligent Surfaces
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Ionizing Radiation Effects in SONOS-Based Neuromorphic Inference Accelerators
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Analog In-Memory Computing for the Synthetic Aperture Radar Polar Format Algorithm
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3663587openalex-snapshot
Hardware-Aware Offline Training of CTT-Based Neuromorphic Hardware
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In-Memory Computing: The Next-Generation AI Computing Paradigm
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Neural Network Compression for Noisy Storage Devices
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Design of An Analog Circuit-Based Artificial Neural Network
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Advancements in Complementary Metal-Oxide Semiconductor-Compatible Tunnel Barrier Engineered Charge-Trapping Synaptic Transistors for Bio-Inspired Neural Networks in Harsh Environments
inferred← citeshttps://doi.org/10.3390/electronics12204291openalex-snapshot
Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection
inferred← citeshttps://doi.org/10.3390/mi10100671openalex-snapshot
Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network
inferred← citeshttps://doi.org/10.3390/s20154222openalex-snapshot
Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks
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FLIVVER: Fly Lobula Inspired Visual Velocity Estimation & Ranging
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A hardware-implemented neural network for the analysis of handwritten numerals
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