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https://doi.org/10.2139/ssrn.4520353

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inferredcites →https://doi.org/10.1016/j.sse.2022.108296openalex-extracted
Back-gate effects on DC performance and carrier transport in 22 nm FDSOI technology down to cryogenic temperatures
inferredcites →https://doi.org/10.1021/acsami.5b08541openalex-extracted
Carbon Nanotube Synaptic Transistor Network for Pattern Recognition
inferredcites →https://doi.org/10.1021/acsnano.8b03831openalex-extracted
Aligned Carbon Nanotube Synaptic Transistors for Large-Scale Neuromorphic Computing
inferredcites →https://doi.org/10.1038/s41699-022-00328-2openalex-extracted
Hexagonal boron nitride (h-BN) memristor arrays for analog-based machine learning hardware
inferredcites →https://doi.org/10.1063/1.4799612openalex-extracted
Impact of back-gate biasing on effective field and mobility in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect-transistors
inferredcites →https://doi.org/10.1063/1.5042468openalex-extracted
Efficient learning and crossbar operations with atomically-thin 2-D material compound synapses
inferredcites →https://doi.org/10.1088/2053-1583/acdfe1openalex-extracted
Dot-product computation and logistic regression with 2D hexagonal-boron nitride (h-BN) memristor arrays
inferredcites →https://doi.org/10.1109/cicc.2017.7993629openalex-extracted
Analog in-memory subthreshold deep neural network accelerator
inferredcites →https://doi.org/10.1109/dac.2018.8465818openalex-extracted
On-Chip Deep Neural Network Storage with Multi-Level eNVM
inferredcites →https://doi.org/10.1109/eurosoi-ulis53016.2021.9560181openalex-extracted
In-depth Cryogenic Characterization of 22 nm FDSOI Technology for Quantum Computation
inferredcites →https://doi.org/10.1109/eurosoi-ulis53016.2021.9560182openalex-extracted
Impact of the Backgate on the Performance of SOI UTBB nMOSFETs at Cryogenic Temperatures
inferredcites →https://doi.org/10.1109/iedm.2015.7409625openalex-extracted
Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)
inferredcites →https://doi.org/10.1109/iedm.2016.7838029openalex-extracted
22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications
inferredcites →https://doi.org/10.1109/iedm13553.2020.9372006openalex-extracted
Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures
inferredcites →https://doi.org/10.1109/iedm45625.2022.10019527openalex-extracted
Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology
inferredcites →https://doi.org/10.1109/iirw.2012.6468962openalex-extracted
Modeling of hot-carrier degradation: Physics and controversial issues
inferredcites →https://doi.org/10.1109/irps.2013.6532037openalex-extracted
Bias temperature instability and hot carrier circuit ageing simulations specificities in UTBB FDSOI 28nm node
inferredcites →https://doi.org/10.1109/irps.2015.7112816openalex-extracted
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
inferredcites →https://doi.org/10.1109/irps.2017.7936296openalex-extracted
Ultrafast pulse characterization of hot carrier injection effects on ballistic carrier transport for sub-100 nm MOSFETs
inferredcites →https://doi.org/10.1109/irps48203.2023.10117718openalex-extracted
Influence of Back Gate Bias on the Hot Carrier Reliability of DSOI nMOSFET
inferredcites →https://doi.org/10.1109/isscc.2018.8310399openalex-extracted
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study
inferredcites →https://doi.org/10.1109/jssc.2021.3098671openalex-extracted
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process
inferredcites →https://doi.org/10.1109/jssc.2022.3140414openalex-extracted
HERMES-Core—A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
inferredcites →https://doi.org/10.1109/jssc.2022.3163197openalex-extracted
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
inferredcites →https://doi.org/10.1109/jxcdc.2021.3098469openalex-extracted
Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications
inferredcites →https://doi.org/10.1109/jxcdc.2021.3123783openalex-extracted
Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling
inferredcites →https://doi.org/10.1109/led.2013.2262521openalex-extracted
Observation of Normally Distributed Energies for Interface Trap Recovery After Hot-Carrier Degradation
inferredcites →https://doi.org/10.1109/led.2015.2504952openalex-extracted
The Impact of Self-Heating on Charge Trapping in High- $k$ -Metal-Gate nFETs
inferredcites →https://doi.org/10.1109/led.2016.2616133openalex-extracted
System On Microheater for On-Chip Annealing of Defects Generated by Hot-Carrier Injection, Bias Temperature Instability, and Ionizing Radiation
inferredcites →https://doi.org/10.1109/led.2016.2633490openalex-extracted
Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies
inferredcites →https://doi.org/10.1109/led.2017.2700326openalex-extracted
Monolithically Integrated Microheater for On-Chip Annealing of Oxide Defects
inferredcites →https://doi.org/10.1109/led.2017.2723319openalex-extracted
Unsupervised Learning Using Charge-Trap Transistors
inferredcites →https://doi.org/10.1109/led.2019.2919871openalex-extracted
Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies
inferredcites →https://doi.org/10.1109/led.2019.2930212openalex-extracted
Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights
inferredcites →https://doi.org/10.1109/mcas.2021.3092533openalex-extracted
Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
inferredcites →https://doi.org/10.1109/tcad.2018.2859237openalex-extracted
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
inferredcites →https://doi.org/10.1109/ted.2012.2186968openalex-extracted
Virtual-Source-Based Self-Consistent Current and Charge FET Models: From Ballistic to Drift-Diffusion Velocity-Saturation Operation
inferredcites →https://doi.org/10.1109/ted.2013.2283253openalex-extracted
Compact Models and the Physics of Nanoscale FETs
inferredcites →https://doi.org/10.1109/ted.2020.3022607openalex-extracted
Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance
inferredcites →https://doi.org/10.1109/ted.2021.3110464openalex-extracted
SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge
inferredcites →https://doi.org/10.1109/ted.2022.3142650openalex-extracted
Cryogenic Characterization and Analysis of Nanoscale SOI FETs Using a Virtual Source Model
inferredcites →https://doi.org/10.1109/ted.2022.3199328openalex-extracted
Impact of Back-Gate Biasing on the Transport Properties of 22 nm FD-SOI MOSFETs at Cryogenic Temperatures
inferredcites →https://doi.org/10.1109/ted.2023.3265939openalex-extracted
Low-Frequency and Random Telegraph Noise in 14-nm Bulk Si Charge-Trap Transistors
inferredcites →https://doi.org/10.1109/tnn.2002.1000139openalex-extracted
Competitive learning with floating-gate circuits
inferredcites →https://doi.org/10.1109/tns.2021.3066612openalex-extracted
Total-Ionizing-Dose Response of Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors
inferredcites →https://doi.org/10.1109/vlsic.2016.7573462openalex-extracted
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
inferredcites →https://doi.org/10.1145/3195970.3196083openalex-extracted
On-chip deep neural network storage with multi-level eNVM
inferredcites →https://doi.org/10.23919/vlsit.2019.8776510openalex-extracted
Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond
inferredcites →https://doi.org/10.48550/arxiv.1709.06614openalex-extracted
inferredcites →https://doi.org/10.48550/arxiv.1902.09417openalex-extracted
Ultra-low Energy charge trap flash based synapse enabled by parasitic leakage mitigation
inferredcites →https://doi.org/10.7567/jjap.52.040001openalex-extracted
Review of Emerging New Solid-State Non-Volatile Memories
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