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80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
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inferred← citeshttps://doi.org/10.1002/9781119298922.ch3openalex-snapshot
Embedded Flash and EEPROM for Smart IoT
inferred← citeshttps://doi.org/10.1007/978-3-031-16344-9_3openalex-snapshot
Flash: A “Forgotten” Technology in VLSI Design
inferred← citeshttps://doi.org/10.1016/j.sse.2023.108783openalex-snapshot
Evidence of Transport Degradation in 22 nm FD-SOI Charge Trapping Transistors for Neural Network Applications
inferred← citeshttps://doi.org/10.1109/iedm45625.2022.10019527openalex-snapshot
Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology
inferred← citeshttps://doi.org/10.1109/irps.2017.7936386openalex-snapshot
MTPM ramped programming optimization methodology
inferred← citeshttps://doi.org/10.1109/isqed.2018.8357278openalex-snapshot
Network on interconnect fabric
inferred← citeshttps://doi.org/10.1109/jssc.2017.2784760openalex-snapshot
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
inferred← citeshttps://doi.org/10.1109/jxcdc.2021.3098469openalex-snapshot
Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications
inferred← citeshttps://doi.org/10.1109/led.2016.2633490openalex-snapshot
Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies
inferred← citeshttps://doi.org/10.1109/led.2017.2723319openalex-snapshot
Unsupervised Learning Using Charge-Trap Transistors
inferred← citeshttps://doi.org/10.1109/led.2019.2930212openalex-snapshot
Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights
inferred← citeshttps://doi.org/10.1109/sispad66650.2025.11186318openalex-snapshot
A Physics-Based Program-Retention Joint Model of Charge-Trap Transistor
inferred← citeshttps://doi.org/10.1109/tcad.2018.2859237openalex-snapshot
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
inferred← citeshttps://doi.org/10.1109/ted.2019.2933484openalex-snapshot
Charge-Trap Transistors for CMOS-Only Analog Memory
inferred← citeshttps://doi.org/10.1109/ted.2025.3595113openalex-snapshot
FinFET-Based Logic-Compatible Low-Voltage Linear-Injection Analog Memory
inferred← citeshttps://doi.org/10.1109/tns.2021.3059594openalex-snapshot
Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors
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