On the public citation graph
Wear rate leveling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/nav.3800020109openalex-snapshot
The Hungarian method for the assignment problem
inferredcites →https://doi.org/10.1109/isscc.2007.373499openalex-snapshot
A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput
inferredcites →https://doi.org/10.1109/jssc.2006.888349openalex-snapshot
A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation
inferredcites →https://doi.org/10.1109/pact.2009.30openalex-snapshot
Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures
inferredcites →https://doi.org/10.1109/relphy.2005.1493077openalex-snapshot
Reliability investigations for manufacturable high density PRAM
inferredcites →https://doi.org/10.1145/1366110.1366204openalex-snapshot
A low-power phase change memory based hybrid cache architecture
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/1555815.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1669112.1669116openalex-snapshot
Characterizing and mitigating the impact of process variations on phase change based memory systems
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1735970.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1736020.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/589411.589415openalex-snapshot
Statistical timing analysis using bounds and selective enumeration
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-42234-9_10openalex-snapshot
Write Mode Aware Loop Tiling for High-Performance Low-Power Volatile PCM in Embedded Systems
inferred← citeshttps://doi.org/10.1007/s00607-015-0464-7openalex-snapshot
Energy-aware assignment and scheduling for hybrid main memory in embedded systems
inferred← citeshttps://doi.org/10.1007/s11390-015-1509-2openalex-snapshot
A Survey of Phase Change Memory Systems
inferred← citeshttps://doi.org/10.1007/s11859-016-1187-0openalex-snapshot
Endurance awarded compiling optimization
inferred← citeshttps://doi.org/10.1016/j.future.2018.02.038openalex-snapshot
DWARM: A wear-aware memory management scheme for in-memory file systems
inferred← citeshttps://doi.org/10.1016/j.memori.2022.100014openalex-snapshot
Gray counters for non-volatile memories
inferred← citeshttps://doi.org/10.1016/j.microrel.2021.114154openalex-snapshot
DLBF: A low overhead wear leveling algorithm for embedded systems with hybrid memory
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.06.003openalex-snapshot
LASER: Latency-Aware Segment Relocation for non-volatile memory
inferred← citeshttps://doi.org/10.1088/2631-8695/ad0fc4openalex-snapshot
OML-PCM: optical multi-level phase change memory architecture for embedded computing systems
inferred← citeshttps://doi.org/10.1109/access.2022.3225193openalex-snapshot
Improving NVM Lifetime Using Task Stack Migration on Low-End MCU-Based Devices
inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045418openalex-snapshot
Software-Based Memory Analysis Environments for In-Memory Wear-Leveling
inferred← citeshttps://doi.org/10.1109/dac.2014.6881363openalex-snapshot
SLC-enabled wear leveling for MLC PCM considering process variation
inferred← citeshttps://doi.org/10.1109/dac.2018.8465824openalex-snapshot
A Collaborative Defense Against Wear Out Attacks in Non-Volatile Processors
inferred← citeshttps://doi.org/10.1109/dac.2018.8465896openalex-snapshot
Wear Leveling for Crossbar Resistive Memory
inferred← citeshttps://doi.org/10.1109/date.2012.6176713openalex-snapshot
Bloom filter-based dynamic wear leveling for phase-change RAM
inferred← citeshttps://doi.org/10.1109/iiki.2016.22openalex-snapshot
Hybrid-LRU Caching Scheme for PDRAM Hybrid Memory Architecture in Cloud Computing
inferred← citeshttps://doi.org/10.1109/ipdps.2016.22openalex-snapshot
Security RBSG: Protecting Phase Change Memory with Security-Level Adjustable Dynamic Mapping
inferred← citeshttps://doi.org/10.1109/isce.2014.6884311openalex-snapshot
Wear-leveling scheduler for phase-change RAM main memory for mobile consumer electronics
inferred← citeshttps://doi.org/10.1109/nanoarch.2014.6880482openalex-snapshot
Compression architecture for bit-write reduction in non-volatile memory technologies
inferred← citeshttps://doi.org/10.1109/nvmsa53655.2021.9628460openalex-snapshot
OCTO+: Optimized Checkpointing of B+ Trees for Non-Volatile Main Memory Wear-Leveling
inferred← citeshttps://doi.org/10.1109/tc.2015.2479605openalex-snapshot
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2015.2506555openalex-snapshot
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory
inferred← citeshttps://doi.org/10.1109/tc.2020.3002537openalex-snapshot
Contour: A Process Variation Aware Wear-Leveling Mechanism for Inodes of Persistent Memory File Systems
inferred← citeshttps://doi.org/10.1109/tc.2021.3126156openalex-snapshot
SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories
inferred← citeshttps://doi.org/10.1109/tcad.2014.2341922openalex-snapshot
Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems
inferred← citeshttps://doi.org/10.1109/tcad.2014.2376989openalex-snapshot
Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation
inferred← citeshttps://doi.org/10.1109/tmscs.2015.2498549openalex-snapshot
Hybrid Main Memory for High Bandwidth Multi-Core System
inferred← citeshttps://doi.org/10.1109/tpds.2016.2586059openalex-snapshot
Durable Address Translation in PCM-based Flash Storage Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2350073openalex-snapshot
Dynamic Wear Leveling for Phase-Change Memories With Endurance Variations
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2360801openalex-snapshot
Two-Port PCM Architecture for Network Processing
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2395415openalex-snapshot
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2467157openalex-snapshot
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3090476openalex-snapshot
PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems
inferred← citeshttps://doi.org/10.1142/s0218126622500669openalex-snapshot
Tnvmalloc: A Thread-Level-Based Wear-Aware Allocator for Nonvolatile Main Memory
inferred← citeshttps://doi.org/10.1145/2086696.2086732openalex-snapshot
Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems
inferred← citeshttps://doi.org/10.1145/2228360.2228520openalex-snapshot
Write performance improvement by hiding R drift latency in phase-change RAM
inferred← citeshttps://doi.org/10.1145/2558427openalex-snapshot
Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
inferred← citeshttps://doi.org/10.1145/2593069.2593217openalex-snapshot
SLC-enabled Wear Leveling for MLC PCM Considering Process Variation
inferred← citeshttps://doi.org/10.1145/2847254openalex-snapshot
Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore Systems
inferred← citeshttps://doi.org/10.1145/2871167openalex-snapshot
A Survey of Architectural Techniques for Managing Process Variation
inferred← citeshttps://doi.org/10.1145/2893186openalex-snapshot
Rethinking Computer Architectures and Software Systems for Phase-Change Memory
inferred← citeshttps://doi.org/10.1145/2905364openalex-snapshot
Improving PCM Endurance with a Constant-Cost Wear Leveling Design
inferred← citeshttps://doi.org/10.1145/3483839openalex-snapshot
Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory
inferred← citeshttps://doi.org/10.1145/3533252openalex-snapshot
Architecting Optically Controlled Phase Change Memory
inferred← citeshttps://doi.org/10.23919/date.2017.7927251openalex-snapshot
Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss
inferred← citeshttps://doi.org/10.48550/arxiv.2004.03244openalex-snapshot
SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory
inferred← citeshttps://doi.org/10.5555/2492708.2493079openalex-snapshot
Bloom filter-based dynamic wear leveling for phase-change RAM
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