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Post-silicon platform for the functional diagnosis and debug of networks-on-chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-92990-1_21openalex-snapshot
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
inferredcites →https://doi.org/10.1109/54.895008openalex-snapshot
Postsilicon validation methodology for microprocessors
inferredcites →https://doi.org/10.1109/ats.2008.15openalex-snapshot
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC
inferredcites →https://doi.org/10.1109/cis.2011.334openalex-snapshot
Fast Verification of Memory Consistency for Chip Multi-Processor
inferredcites →https://doi.org/10.1109/dsd.2006.81openalex-snapshot
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
inferredcites →https://doi.org/10.1109/hldvt.2004.1431260openalex-snapshot
An event-based network-on-chip monitoring service
inferredcites →https://doi.org/10.1109/hpca.2009.4798252openalex-snapshot
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
inferredcites →https://doi.org/10.1109/hpca.2009.4798278openalex-snapshot
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942108openalex-snapshot
Proceedings of the 2019 International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/iccd.2008.4751878openalex-snapshot
Reversi: Post-silicon validation system for modern microprocessors
inferredcites →https://doi.org/10.1109/iccd.2008.4751884openalex-snapshot
Post-silicon verification for cache coherence
inferredcites →https://doi.org/10.1109/ies.2006.357464openalex-snapshot
Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective
inferredcites →https://doi.org/10.1109/l-ca.2008.9openalex-snapshot
Transaction-Aware Network-on-Chip Resource Reservation
inferredcites →https://doi.org/10.1109/mdt.2008.77openalex-snapshot
In-System Silicon Validation and Debug
inferredcites →https://doi.org/10.1109/sc.2010.15openalex-snapshot
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors
inferredcites →https://doi.org/10.1109/tc.2010.123openalex-snapshot
Compressing Cache State for Postsilicon Processor Debug
inferredcites →https://doi.org/10.1109/tcad.2009.2030595openalex-snapshot
Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)
inferredcites →https://doi.org/10.1109/tcsi.2009.2034887openalex-snapshot
On-Chip Support for NoC-Based SoC Debugging
inferredcites →https://doi.org/10.1109/test.1995.529812openalex-snapshot
Proceedings of 1995 IEEE International Test Conference (ITC)
inferredcites →https://doi.org/10.1109/test.2001.966625openalex-snapshot
Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip
inferredcites →https://doi.org/10.1109/test.2010.5699214openalex-snapshot
Automated trace signals selection using the RTL descriptions
inferredcites →https://doi.org/10.1109/vdat.2009.5158125openalex-snapshot
A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs
inferredcites →https://doi.org/10.1109/vlsisoc.2010.5642623openalex-snapshot
Enhancing post-silicon processor debug with Incremental Cache state Dumping
inferredcites →https://doi.org/10.1109/vts.2009.51openalex-snapshot
Automated Selection of Signals to Observe for Efficient Silicon Debug
inferredcites →https://doi.org/10.1145/1146909.1146916openalex-snapshot
A reconfigurable design-for-debug infrastructure for SoCs
inferredcites →https://doi.org/10.1145/1176254.1176275openalex-snapshot
Bounded arbitration algorithm for QoS-supported on-chip communication
inferredcites →https://doi.org/10.1145/1403375.1403689openalex-snapshot
Automated trace signals identification and state restoration for improving observability in post-silicon validation
inferredcites →https://doi.org/10.1145/1629911.1629952openalex-snapshot
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
inferredcites →https://doi.org/10.1145/1929943.1929946openalex-snapshot
Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip
inferredcites →https://doi.org/10.1145/2155620.2155630openalex-snapshot
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
inferredcites →https://doi.org/10.1145/2155620.2155668openalex-snapshot
Formally enhanced runtime verification to ensure NoC functional correctness
inferredcites →https://doi.org/10.1145/359545.359563openalex-snapshot
Time, clocks, and the ordering of events in a distributed system
inferredcites →https://doi.org/10.5220/0003942204500458openalex-snapshot
SELF-ADAPTIVE NOC POWER MANAGEMENT WITH DUAL-LEVEL AGENTS - Architecture and Implementation
inferredcites →https://doi.org/10.5555/1874620.1874670openalex-snapshot
Cache aware compression for processor debug support
inferredcites →https://doi.org/10.5555/1874620.1874942openalex-snapshot
Trace signal selection for visibility enhancement in post-silicon validation
inferredcites →https://doi.org/10.5555/2132325.2132461openalex-snapshot
Simulation-based signal selection for state restoration in silicon debug
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_13openalex-snapshot
NoC Post-Silicon Validation and Debug
inferred← citeshttps://doi.org/10.1016/j.vlsi.2015.10.002openalex-snapshot
Design and implementation of multi-mode routers for large-scale inter-core networks
inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045570openalex-snapshot
Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs
inferred← citeshttps://doi.org/10.1109/socc46988.2019.1570548502openalex-snapshot
Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation
inferred← citeshttps://doi.org/10.1109/tc.2016.2628058openalex-snapshot
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2021.3069968openalex-snapshot
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty
inferred← citeshttps://doi.org/10.1109/tcad.2020.3044897openalex-snapshot
WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip
inferred← citeshttps://doi.org/10.1109/tetc.2022.3203611openalex-snapshot
ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC Based MPSoCs
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2803478openalex-snapshot
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2827928openalex-snapshot
Reusing Trace Buffers as Victim Caches
inferred← citeshttps://doi.org/10.1109/vlsid.2016.14openalex-snapshot
Symptomatic Bug Localization for Functional Debug of Hardware Designs
inferred← citeshttps://doi.org/10.1145/3291532openalex-snapshot
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/3659102openalex-snapshot
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers
inferred← citeshttps://doi.org/10.12928/telkomnika.v18i3.13174openalex-snapshot
On-chip debugging for microprocessor design
inferred← citeshttps://doi.org/10.23919/date.2017.7927052openalex-snapshot
Reusing trace buffers to enhance cache performance
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