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FlexiBuffer
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/mc.2007.443openalex-snapshot
The Case for Energy-Proportional Computing
inferredcites →https://doi.org/10.1109/micro.2010.48openalex-snapshot
Adaptive Flow Control for Robust Performance and Energy
inferredcites →https://doi.org/10.1109/nocs.2010.10openalex-snapshot
Evaluating Bufferless Flow Control for On-chip Networks
inferredcites →https://doi.org/10.1109/nocs.2010.16openalex-snapshot
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
inferredcites →https://doi.org/10.1145/1013235.1013249openalex-snapshot
Microarchitectural techniques for power gating of execution units
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669145openalex-snapshot
Low-cost router microarchitecture for on-chip networks
inferredcites →https://doi.org/10.1145/871506.871531openalex-snapshot
Leakage power modeling and optimization in interconnection networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-27119-4_14openalex-snapshot
HVCRouter: Energy Efficient Network-on-Chip Router with Heterogeneous Virtual Channels
inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_3openalex-snapshot
CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router
inferred← citeshttps://doi.org/10.1007/978-3-319-31596-6_11openalex-snapshot
Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs
inferred← citeshttps://doi.org/10.1007/978-94-017-7358-4_16-1openalex-snapshot
Network-on-Chip Design
inferred← citeshttps://doi.org/10.1007/s11227-016-1859-8openalex-snapshot
Energy-efficient NoC with multi-granularity power optimization
inferred← citeshttps://doi.org/10.1007/s11227-024-06000-4openalex-snapshot
DBU-PG: energy-efficient noc design using dual-buffering power gating
inferred← citeshttps://doi.org/10.1007/s11432-015-0328-yopenalex-snapshot
Stealth-ACK: stealth transmissions of NoC acknowledgements
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2020.106578openalex-snapshot
ChangeSUB: A power efficient multiple network-on-chip architecture
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.01.016openalex-snapshot
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers
inferred← citeshttps://doi.org/10.1016/j.mejo.2024.106234openalex-snapshot
SPONGE+: A NoC-based power gating scheme for overall router column opening and closing control
inferred← citeshttps://doi.org/10.1049/el.2013.3225openalex-snapshot
Power‐gating technique for network‐on‐chip buffers
inferred← citeshttps://doi.org/10.1080/00207217.2015.1104728openalex-snapshot
Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating
inferred← citeshttps://doi.org/10.1109/ats.2018.00036openalex-snapshot
Dynamic Fine-Grain Power Gating Design in WiNoC
inferred← citeshttps://doi.org/10.1109/dac.2014.6881489openalex-snapshot
Power-aware NoCs through routing and topology reconfiguration
inferred← citeshttps://doi.org/10.1109/dsd.2014.28openalex-snapshot
Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522345openalex-snapshot
Energy-efficient interconnect via Router Parking
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657068openalex-snapshot
SLIDER: Smart Late Injection DEflection Router for mesh NoCs
inferred← citeshttps://doi.org/10.1109/icis.2017.7960009openalex-snapshot
NoC power optimization using combined routing algorithms
inferred← citeshttps://doi.org/10.1109/igcc.2015.7393682openalex-snapshot
Power- and performance-aware fine-grained reconfigurable router architecture for NoC
inferred← citeshttps://doi.org/10.1109/ipdps.2017.77openalex-snapshot
Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/isca.2018.00065openalex-snapshot
TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks
inferred← citeshttps://doi.org/10.1109/islped.2019.8824806openalex-snapshot
Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers
inferred← citeshttps://doi.org/10.1109/isqed.2016.7479205openalex-snapshot
Power efficient router architecture for wireless Network-on-Chip
inferred← citeshttps://doi.org/10.1109/nocs.2014.7008767openalex-snapshot
Variable-width datapath for on-chip network static power reduction
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579326openalex-snapshot
TooT: an efficient and scalable power-gating method for NoC routers
inferred← citeshttps://doi.org/10.1109/tc.2012.201openalex-snapshot
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs
inferred← citeshttps://doi.org/10.1109/tc.2020.3033163openalex-snapshot
A Voting Approach for Adaptive Network-on-Chip Power-Gating
inferred← citeshttps://doi.org/10.1109/tcad.2020.3007555openalex-snapshot
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012170openalex-snapshot
Aggressive Fine-Grained Power Gating of NoC Buffers
inferred← citeshttps://doi.org/10.1109/tpds.2014.2345065openalex-snapshot
FreeRider: Non-Local Adaptive Network-on-Chip Routing with Packet-Carried Propagation of Congestion Information
inferred← citeshttps://doi.org/10.1109/tsusc.2017.2742219openalex-snapshot
Adaptive Multi-Voltage Scaling with Utilization Prediction for Energy-Efficient Wireless NoC
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2383442openalex-snapshot
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip
inferred← citeshttps://doi.org/10.1109/vlsid.2015.86openalex-snapshot
Smart Port Allocation for Adaptive NoC Routers
inferred← citeshttps://doi.org/10.1109/vlsid.2017.42openalex-snapshot
Energy-Efficient Transceiver for Wireless NoC
inferred← citeshttps://doi.org/10.1109/vlsid.2018.93openalex-snapshot
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs
inferred← citeshttps://doi.org/10.1142/s021812662450172xopenalex-snapshot
Applying SMART-Based Power Gating Approach in NoC System
inferred← citeshttps://doi.org/10.1145/2567936openalex-snapshot
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
inferred← citeshttps://doi.org/10.1145/2593069.2593187openalex-snapshot
Power-Aware NoCs through Routing and Topology Reconfiguration
inferred← citeshttps://doi.org/10.1145/2897937.2897963openalex-snapshot
A low-cost conflict-free NoC for GPGPUs
inferred← citeshttps://doi.org/10.1145/3130218.3130220openalex-snapshot
A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip
inferred← citeshttps://doi.org/10.1145/3529106openalex-snapshot
A Segmented Adaptive Router for Near Energy-Proportional Networks-on-Chip
inferred← citeshttps://doi.org/10.23919/date.2017.7927203openalex-snapshot
Machine learning enabled power-aware Network-on-Chip design
inferred← citeshttps://doi.org/10.3850/9783981537079_0710openalex-snapshot
Adaptive Multi-Voltage Scaling in Wireless NoC for High Performance Low Power Applications
inferred← citeshttps://doi.org/10.4018/978-1-7998-4610-9.ch003openalex-snapshot
Macro and Micro Architectures for Network on Chip
inferred← citeshttps://doi.org/10.5555/2485288.2485665openalex-snapshot
DeBAR: deflection based adaptive router with minimal buffering
inferred← citeshttps://doi.org/10.5555/2755753.2757101openalex-snapshot
Malleable NoC: dark silicon inspired adaptable Network-on-Chip
inferred← citeshttps://doi.org/10.5555/2755753.2757164openalex-snapshot
An energy-efficient virtual channel power-gating mechanism for on-chip networks
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