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Endurance-aware cache line management for non-volatile caches
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0021-9991(81)90227-8openalex-snapshot
A very fast shift-register sequence random number generator
inferredcites →https://doi.org/10.1038/nmat2023openalex-snapshot
Nanoionics-based resistive switching memories
inferredcites →https://doi.org/10.1038/nnano.2008.160openalex-snapshot
Memristive switching mechanism for metal/oxide/metal nanodevices
inferredcites →https://doi.org/10.1063/1.3524521openalex-snapshot
High switching endurance in TaOx memristive devices
inferredcites →https://doi.org/10.1109/date.2004.1268792openalex-snapshot
Proceedings Design, Automation and Test in Europe Conference and Exhibition
inferredcites →https://doi.org/10.1109/date.2010.5457221openalex-snapshot
Energy- and endurance-aware design of phase change memory caches
inferredcites →https://doi.org/10.1109/hpca.2011.5749752openalex-snapshot
FREE-p: Protecting non-volatile memory against both hard and soft errors
inferredcites →https://doi.org/10.1109/iccd.2005.2openalex-snapshot
Proceedings. 2005 International Conference on Computer Design
inferredcites →https://doi.org/10.1109/iccd.2007.4601934openalex-snapshot
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
inferredcites →https://doi.org/10.1109/iedm.1995openalex-snapshot
Proceedings of International Electron Devices Meeting
inferredcites →https://doi.org/10.1109/iedm.2009.5424408openalex-snapshot
High density and ultra small cell size of Contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits
inferredcites →https://doi.org/10.1109/iedm.2010.5703395openalex-snapshot
Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance
inferredcites →https://doi.org/10.1109/iedm.2011.6131539openalex-snapshot
Physical mechanisms of endurance degradation in TMO-RRAM
inferredcites →https://doi.org/10.1109/isscc.2011.5746281openalex-snapshot
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
inferredcites →https://doi.org/10.1109/l-ca.2010.2openalex-snapshot
A Phase Change Memory as a Secure Main Memory
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/micro.2010.33openalex-snapshot
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
inferredcites →https://doi.org/10.1109/micro.2010.46openalex-snapshot
SAFER: Stuck-At-Fault Error Recovery for Memories
inferredcites →https://doi.org/10.1109/relphy.1996openalex-snapshot
Proceedings of International Reliability Physics Symposium
inferredcites →https://doi.org/10.1109/relphy.2005.1493077openalex-snapshot
Reliability investigations for manufacturable high density PRAM
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1109/tvlsi.2012.2220791openalex-snapshot
Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
inferredcites →https://doi.org/10.1137/0215025openalex-snapshot
A Simple Unpredictable Pseudo-Random Number Generator
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1735970.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1736020.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1815961.1815980openalex-snapshot
Use ECP, not ECC, for hard failures in resistive memories
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/871506.871511openalex-snapshot
A forward body-biased low-leakage SRAM cache
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-18026-3_5openalex-snapshot
Compilation and Wear Leveling for Programmable Logic-in-Memory Architecture
inferred← citeshttps://doi.org/10.1007/978-3-030-19262-4_3openalex-snapshot
In-Memory Computing: The Integration of Storage and Processing
inferred← citeshttps://doi.org/10.1007/978-3-031-42478-6_2openalex-snapshot
An Overview of Computation-in-Memory (CIM) Architectures
inferred← citeshttps://doi.org/10.1007/s10766-016-0436-3openalex-snapshot
Optimization of Data Allocation on CMP Embedded System with Data Migration
inferred← citeshttps://doi.org/10.1007/s11227-019-02758-0openalex-snapshot
Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits
inferred← citeshttps://doi.org/10.1016/j.microrel.2023.114939openalex-snapshot
Enhancing the lifetime of STT-RAM using compression based wear leveling technique
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.06.003openalex-snapshot
LASER: Latency-Aware Segment Relocation for non-volatile memory
inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045162openalex-snapshot
The Power of Computation-in-Memory Based on Memristive Devices
inferred← citeshttps://doi.org/10.1109/icnc.2015.7378130openalex-snapshot
Task data Optimization allocation with Data Migration
inferred← citeshttps://doi.org/10.1145/3350755.3400274openalex-snapshot
Closing the Gap Between Cache-oblivious and Cache-adaptive Analysis
inferred← citeshttps://doi.org/10.1145/3357526.3357554openalex-snapshot
A computation-in-memory accelerator based on resistive devices
inferred← citeshttps://doi.org/10.1145/3365837openalex-snapshot
A Classification of Memory-Centric Computing
inferred← citeshttps://doi.org/10.1145/3451995openalex-snapshot
An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory
inferred← citeshttps://doi.org/10.1145/3544974openalex-snapshot
A Survey on Memory-centric Computer Architectures
inferred← citeshttps://doi.org/10.1145/3629524openalex-snapshot
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing
inferred← citeshttps://doi.org/10.1145/3653452openalex-snapshot
POEM: Performance Optimization and Endurance Management for Non-volatile Caches
inferred← citeshttps://doi.org/10.23919/date.2017.7927152openalex-snapshot
Endurance management for resistive Logic-In-Memory computing architectures
inferred← citeshttps://doi.org/10.24251/hicss.2021.870openalex-snapshot
Neverlast: Towards the Design and Implementation of the NVM-based Everlasting Operating System
inferred← citeshttps://doi.org/10.3390/jlpea6010001openalex-snapshot
A Technique for Improving Lifetime of Non-Volatile Caches Using Write-Minimization
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