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An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11227-019-02758-0openalex-snapshot
Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits
inferredcites →https://doi.org/10.1109/aspdac.2015.7059057openalex-snapshot
Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy
inferredcites →https://doi.org/10.1109/hotchips.2011.7477494openalex-snapshot
Hybrid memory cube (HMC)
inferredcites →https://doi.org/10.1109/hpca.2016.7446068openalex-snapshot
Efficient footprint caching for Tagless DRAM Caches
inferredcites →https://doi.org/10.1109/iccd.2011.6081427openalex-snapshot
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems
inferredcites →https://doi.org/10.1109/iscas.2007.377981openalex-snapshot
A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme
inferredcites →https://doi.org/10.1109/ispass.2005.1430546openalex-snapshot
ISPASS 2005 IEEE International Symposium on Performance Analysis of Systems and Software
inferredcites →https://doi.org/10.1109/isscc.2011.5746413openalex-snapshot
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking
inferredcites →https://doi.org/10.1109/isscc.2014.6757501openalex-snapshot
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV
inferredcites →https://doi.org/10.1109/mdt.2010.97openalex-snapshot
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing
inferredcites →https://doi.org/10.1109/micro.2012.30openalex-snapshot
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
inferredcites →https://doi.org/10.1109/micro.2012.31openalex-snapshot
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
inferredcites →https://doi.org/10.1109/micro.2014.36openalex-snapshot
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth
inferredcites →https://doi.org/10.1109/micro.2014.51openalex-snapshot
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
inferredcites →https://doi.org/10.1109/mm.2016.25openalex-snapshot
Knights Landing: Second-Generation Intel Xeon Phi Product
inferredcites →https://doi.org/10.1109/nvmsa.2015.7304363openalex-snapshot
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1109/tc.2015.2435772openalex-snapshot
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture
inferredcites →https://doi.org/10.1109/tc.2016.2557326openalex-snapshot
Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches
inferredcites →https://doi.org/10.1109/vlsi-soc.2015.7314437openalex-snapshot
Filtering dirty data in DRAM to reduce PRAM writes
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555815.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555815.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2024724.2024738openalex-snapshot
Power management of hybrid DRAM/PRAM-based main memory
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2228360.2228374openalex-snapshot
Coding-based energy minimization for phase change memory
inferredcites →https://doi.org/10.1145/2508148.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/2579671openalex-snapshot
Endurance-aware cache line management for non-volatile caches
inferredcites →https://doi.org/10.1145/2872887.2750383openalex-snapshot
A fully associative, tagless DRAM cache
inferredcites →https://doi.org/10.1145/2905364openalex-snapshot
Improving PCM Endurance with a Constant-Cost Wear Leveling Design
inferredcites →https://doi.org/10.1145/3190856openalex-snapshot
Self-Adaptive Filtering Algorithm with PCM-Based Memory Storage System
inferredcites →https://doi.org/10.1145/3338505openalex-snapshot
Morphable DRAM Cache Design for Hybrid Memory Systems
inferredcites →https://doi.org/10.5555/1950815.1950867openalex-snapshot
A frequent-value based PRAM memory architecture
inferredcites →https://doi.org/10.5555/2840819.2840823openalex-snapshot
A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10619-022-07421-xopenalex-snapshot
Challenges and future directions for energy, latency, and lifetime improvements in NVMs
inferred← citeshttps://doi.org/10.1007/s11390-023-2561-yopenalex-snapshot
P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
inferred← citeshttps://doi.org/10.1016/j.future.2023.08.013openalex-snapshot
Wear-leveling-aware buddy-like memory allocator for persistent memory file systems
inferred← citeshttps://doi.org/10.1016/j.future.2025.108332openalex-snapshot
Log-Tree: Building log-enhanced B + -tree for hybrid DRAM/PM main memories
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103406openalex-snapshot
Optimizing both performance and tail latency for B + tree on persistent memory
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103543openalex-snapshot
WEnSIBR: Compression using dynamic bases supported with encoding and zone wise wear leveling for NVMs
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103892openalex-snapshot
A History-vector based Encryption strategy to improve lifetime of Non-Volatile Main Memory
inferred← citeshttps://doi.org/10.1049/ell2.13304openalex-snapshot
A case study on integrating energy‐efficient technologies for display devices
inferred← citeshttps://doi.org/10.1049/ipr2.12993openalex-snapshot
A feasibility analysis of image approximation with image quality assessments
inferred← citeshttps://doi.org/10.1063/5.0133358openalex-snapshot
Analysis of power-performance trade-offs in DRAM-NVM based hybrid main memory
inferred← citeshttps://doi.org/10.1109/access.2024.3512176openalex-snapshot
A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems
inferred← citeshttps://doi.org/10.1109/imeta62882.2024.10808148openalex-snapshot
Node Hibernation Optimization Strategy for Metaverse Stream Computing
inferred← citeshttps://doi.org/10.1109/tcad.2024.3446720openalex-snapshot
NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy
inferred← citeshttps://doi.org/10.1109/tcad.2025.3642196openalex-snapshot
WPAlloc: An Efficient Wear-Leveling-Aware Parallel Allocator for Persistent Memory File Systems
inferred← citeshttps://doi.org/10.1109/tmag.2023.3267467openalex-snapshot
MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs
inferred← citeshttps://doi.org/10.1109/vlsid64188.2025.00059openalex-snapshot
PAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main Memories
inferred← citeshttps://doi.org/10.1145/3568923.3568926openalex-snapshot
Design of Intelligent Information Platform for College Students' Volunteer Service Based on Mobile Platform
inferred← citeshttps://doi.org/10.1145/3589327openalex-snapshot
Hamming Tree: The Case for Energy-Aware Indexing for NVMs
inferred← citeshttps://doi.org/10.1145/3653452openalex-snapshot
POEM: Performance Optimization and Endurance Management for Non-volatile Caches
inferred← citeshttps://doi.org/10.1145/3812550openalex-snapshot
EnVector: Encoding using Pattern based Vectors for Energy Efficient Non-Volatile Main Memories
inferred← citeshttps://doi.org/10.1145/3832810.3832852openalex-snapshot
HGB+-Tree: An Hourglass-like B+-tree for Persistent Memory
inferred← citeshttps://doi.org/10.1186/s13638-025-02506-4openalex-snapshot
Enhancing reliability of 3D portable SSDs by storing redundant data to RRAM cache considering layer-to-layer process variation
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