On the public citation graph
Gate-Level Information Flow Tracking for Security Lattices
0 signed · 73 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/j.1538-7305.1948.tb00917.xopenalex-snapshot
A Mathematical Theory of Communication
inferredcites →https://doi.org/10.1007/11967668_15openalex-snapshot
Predicting Secret Keys Via Branch Prediction
inferredcites →https://doi.org/10.1007/3-540-68697-5_9openalex-snapshot
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
inferredcites →https://doi.org/10.1007/978-3-658-00333-3_30openalex-snapshot
Building Technologies that Help Cyber-Defense: Hardware-enabled Trust
inferredcites →https://doi.org/10.1007/s10207-010-0115-0openalex-snapshot
A case study in hardware Trojan design and implementation
inferredcites →https://doi.org/10.1016/s0004-3702(99)00035-1openalex-snapshot
Algorithms for selective enumeration of prime implicants
inferredcites →https://doi.org/10.1109/43.402497openalex-snapshot
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
inferredcites →https://doi.org/10.1109/health.2011.6026732openalex-snapshot
Hijacking an insulin pump: Security attacks and defenses for a diabetes therapy system
inferredcites →https://doi.org/10.1109/jproc.2011.2161428openalex-snapshot
Cyber–Physical Security of a Smart Grid Infrastructure
inferredcites →https://doi.org/10.1109/jsac.2002.806121openalex-snapshot
Language-based information-flow security
inferredcites →https://doi.org/10.1109/les.2013.2261572openalex-snapshot
Expanding Gate Level Information Flow Tracking for Multilevel Security
inferredcites →https://doi.org/10.1109/mdt.2013.2247457openalex-snapshot
Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip
inferredcites →https://doi.org/10.1109/sp.1982.10014openalex-snapshot
Security Policies and Security Models
inferredcites →https://doi.org/10.1109/sp.2008.31openalex-snapshot
Pacemakers and Implantable Cardiac Defibrillators: Software Radio Attacks and Zero-Power Defenses
inferredcites →https://doi.org/10.1109/tcad.2011.2120970openalex-snapshot
Theoretical Fundamentals of Gate Level Information Flow Tracking
inferredcites →https://doi.org/10.1109/tcad.2014.2331332openalex-snapshot
Leveraging Gate-Level Properties to Identify Hardware Timing Channels
inferredcites →https://doi.org/10.1145/1024393.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/1037187.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/1294261.1294293openalex-snapshot
Information flow control for standard OS abstractions
inferredcites →https://doi.org/10.1145/1314299.1314302openalex-snapshot
Labels and event processes in the Asbestos operating system
inferredcites →https://doi.org/10.1145/1323293.1294293openalex-snapshot
Information flow control for standard OS abstractions
inferredcites →https://doi.org/10.1145/1508244.1508258openalex-snapshot
Complete information flow tracking from the gates up
inferredcites →https://doi.org/10.1145/2000064.2000087openalex-snapshot
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
inferredcites →https://doi.org/10.1145/2024724.2024782openalex-snapshot
Information flow isolation in I2C and USB
inferredcites →https://doi.org/10.1145/360051.360056openalex-snapshot
A lattice model of secure information flow
inferredcites →https://doi.org/10.1145/596980.596983openalex-snapshot
Information flow inference for ML
inferredcites →https://doi.org/10.1147/rd.92.0090openalex-snapshot
Hazard Detection in Combinational and Sequential Switching Circuits
inferredcites →https://doi.org/10.1184/r1/6468716openalex-snapshot
Dynamic Taint Analysis for Automatic Detection, Analysis, and Signature Generation of Exploits on Commodity Software
inferredcites →https://doi.org/10.3233/jcs-1996-42-304openalex-snapshot
A sound type system for secure flow analysis
inferredcites →https://doi.org/10.5555/353629.353648openalex-snapshot
A sound type system for secure flow analysis
inferredcites →https://doi.org/10.5860/choice.45-3816openalex-snapshot
Digital electronics: principles, devices and applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-40923-3_14openalex-snapshot
Pattern-Based Information Flow Control for Safety-Critical On-Chip Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-58687-3_8openalex-snapshot
Digital Twin for Secure Semiconductor Lifecycle Management
inferred← citeshttps://doi.org/10.1007/978-3-319-79081-7_5openalex-snapshot
Design Techniques for Hardware Trojans Prevention and Detection at the Gate Level
inferred← citeshttps://doi.org/10.1007/s13389-022-00306-wopenalex-snapshot
Isadora: automated information-flow property generation for hardware security verification
inferred← citeshttps://doi.org/10.1007/s41635-023-00141-3openalex-snapshot
EXERTv2: Exhaustive Integrity Analysis for Information Flow Security with FSM Integration
inferred← citeshttps://doi.org/10.1016/j.cose.2018.07.006openalex-snapshot
Symbolic execution based test-patterns generation algorithm for hardware Trojan detection
inferred← citeshttps://doi.org/10.1016/j.cose.2024.104072openalex-snapshot
Hardware information flow tracking based on lightweight path awareness
inferred← citeshttps://doi.org/10.1016/j.mejo.2023.106088openalex-snapshot
The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice
inferred← citeshttps://doi.org/10.1016/j.vlsi.2023.102089openalex-snapshot
Hardware/software security co-verification and vulnerability detection: An information flow perspective
inferred← citeshttps://doi.org/10.1109/access.2017.2780254openalex-snapshot
Towards Quantified Data Analysis of Information Flow Tracking for Secure System Design
inferred← citeshttps://doi.org/10.1109/asianhost56390.2022.10022211openalex-snapshot
EXERT: EXhaustive IntEgRiTy Analysis for Information Flow Security
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473911openalex-snapshot
FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420548openalex-snapshot
GEmFuzz: Uncovering System-Level Vulnerabilities in SoCs via Emulation-Based Grey-Box Fuzzing
inferred← citeshttps://doi.org/10.1109/eurosp68448.2026.00062openalex-snapshot
VerIFI: Formal Verification of Microarchitectural Information-Flow Integrity
inferred← citeshttps://doi.org/10.1109/globecom52923.2024.10901102openalex-snapshot
LUT Level Information Flow Tracking for FPGA Design Security Verification
inferred← citeshttps://doi.org/10.1109/host64725.2025.11050040openalex-snapshot
Evaluating the Effectiveness of Hardware Trojan Detection Approaches at RTL
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323726openalex-snapshot
TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing
inferred← citeshttps://doi.org/10.1109/ivsw.2018.8494858openalex-snapshot
Property Based Formal Security Verification for Hardware Trojan Detection
inferred← citeshttps://doi.org/10.1109/mtv.2017.11openalex-snapshot
Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00032openalex-snapshot
Seeds of SEED: Building and Verifying Foundationally Isolated Hardware Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2020.3047976openalex-snapshot
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
inferred← citeshttps://doi.org/10.1109/test.2017.8242062openalex-snapshot
Hardware trojan detection through information flow security verification
inferred← citeshttps://doi.org/10.1109/tifs.2017.2707323openalex-snapshot
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP—Part I: Framework Fundamentals
inferred← citeshttps://doi.org/10.1145/2732408openalex-snapshot
Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation
inferred← citeshttps://doi.org/10.1145/2902961.2903040openalex-snapshot
Tracking Data Flow at Gate-Level through Structural Checking
inferred← citeshttps://doi.org/10.1145/3037697.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3093315.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3093336.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3093337.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3240765.3243415openalex-snapshot
High-level synthesis with timing-sensitive information flow enforcement
inferred← citeshttps://doi.org/10.1145/3568957openalex-snapshot
Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis
inferred← citeshttps://doi.org/10.1145/3576199openalex-snapshot
Challenges and Opportunities of Security-Aware EDA
inferred← citeshttps://doi.org/10.1145/3676536.3676658openalex-snapshot
HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware
inferred← citeshttps://doi.org/10.1186/s42400-026-00676-2openalex-snapshot
SeqCube-HT: state-cube-guided generation of sequential hardware Trojan benchmarks
inferred← citeshttps://doi.org/10.26599/tst.2019.9010047openalex-snapshot
HTDet: A clustering method using information entropy for hardware Trojan detection
inferred← citeshttps://doi.org/10.3390/electronics11172649openalex-snapshot
Hardware Trojan Detection Using Effective Property-Checking Method
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.