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Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44570-6_9openalex-snapshot
FlexCache: A Framework for Flexible Compiler Generated Data Caching
inferredcites →https://doi.org/10.1007/978-3-540-72521-3_23openalex-snapshot
Optimizing the Use of Static Buffers for DMA on a CELL Chip
inferredcites →https://doi.org/10.1093/comjnl/bxq026openalex-snapshot
Local Memory Design Space Exploration for High-Performance Computing
inferredcites →https://doi.org/10.1109/date.2005.97openalex-snapshot
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access
inferredcites →https://doi.org/10.1109/date.2006.243809openalex-snapshot
An integrated scratch-pad allocator for affine and non-affine code
inferredcites →https://doi.org/10.1109/date.2006.243810openalex-snapshot
Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns
inferredcites →https://doi.org/10.1109/hpca.2009.4798237openalex-snapshot
Design and implementation of software-managed caches for multicores with local memory
inferredcites →https://doi.org/10.1109/ispass.2014.6844487openalex-snapshot
Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs
inferredcites →https://doi.org/10.1109/pact.2005.33openalex-snapshot
Optimizing Compiler for the CELL Processor
inferredcites →https://doi.org/10.1145/1250662.1250707openalex-snapshot
Comparing memory systems for chip multiprocessors
inferredcites →https://doi.org/10.1145/1356058.1356079openalex-snapshot
Prefetching irregular references for software cache on cell
inferredcites →https://doi.org/10.1145/1375527.1375570openalex-snapshot
Orchestrating data transfer for the cell/B.E. processor
inferredcites →https://doi.org/10.1145/1454115.1454156openalex-snapshot
Hybrid access-specific software cache techniques for the cell BE architecture
inferredcites →https://doi.org/10.1145/1582710.1582711openalex-snapshot
Compiler-directed scratchpad memory management via graph coloring
inferredcites →https://doi.org/10.1145/2016604.2016616openalex-snapshot
A reconfigurable cache architecture for energy efficiency
inferredcites →https://doi.org/10.1145/2024724.2024937openalex-snapshot
A reuse-aware prefetching scheme for scratchpad memory
inferredcites →https://doi.org/10.1145/2038698.2038731openalex-snapshot
Vector class on limited local memory (LLM) multi-core processors
inferredcites →https://doi.org/10.1145/2380403.2380440openalex-snapshot
Integrating software caches with scratch pad memory
inferredcites →https://doi.org/10.1145/2749469.2750411openalex-snapshot
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
inferredcites →https://doi.org/10.1145/339647.339685openalex-snapshot
Reconfigurable caches and their application to media processing
inferredcites →https://doi.org/10.1145/360128.360153openalex-snapshot
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
inferredcites →https://doi.org/10.1145/378239.379049openalex-snapshot
Dynamic management of scratch-pad memory space
inferredcites →https://doi.org/10.1145/513829.513858openalex-snapshot
Compiler-directed cache polymorphism
inferredcites →https://doi.org/10.1145/545214.545241openalex-snapshot
Managing multi-configuration hardware via dynamic working set analysis
inferredcites →https://doi.org/10.1145/951710.951747openalex-snapshot
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
inferredcites →https://doi.org/10.1147/rd.494.0589openalex-snapshot
Introduction to the Cell multiprocessor
inferredcites →https://doi.org/10.5555/1898699.1898713openalex-snapshot
Dynamically reconfigurable cache architecture using adaptive block allocation policy
inferredcites →https://doi.org/10.5555/2388996.2389117openalex-snapshot
Hardware-software coherence protocol for the coexistence of caches and local memories
inferredcites →https://doi.org/10.5555/320080.320119openalex-snapshot
Selective cache ways: on-demand cache resource allocation
inferredcites →https://doi.org/10.5555/787260.787762openalex-snapshot
Efficient utilization of scratch-pad memory in embedded processor applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.103022openalex-snapshot
COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
inferred← citeshttps://doi.org/10.1109/ccet50901.2020.9213108openalex-snapshot
DPA: Demand-Based Partition and Data Allocation for Hybrid On-Chip Memory
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00056openalex-snapshot
Static Function Prefetching for Efficient Code Management on Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/les.2017.2748098openalex-snapshot
SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems
inferred← citeshttps://doi.org/10.1109/pdp50117.2020.00026openalex-snapshot
RSMCC: Enabling Ring-based Software Managed Cache-Coherent Embedded SoCs
inferred← citeshttps://doi.org/10.1109/tpds.2022.3154315openalex-snapshot
OSM: Off-Chip Shared Memory for GPUs
inferred← citeshttps://doi.org/10.1145/3629524openalex-snapshot
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing
inferred← citeshttps://doi.org/10.1145/3676641.3716014openalex-snapshot
Practical Federated Recommendation Model Learning Using ORAM with Controlled Privacy
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