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High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4614-6624-6_25-1openalex-snapshot
Equitable Coloring of Graphs
inferredcites →https://doi.org/10.1007/978-3-642-31464-3_29openalex-snapshot
Parallel Community Detection for Massive Graphs
inferredcites →https://doi.org/10.1016/j.jpdc.2014.11.002openalex-snapshot
On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms
inferredcites →https://doi.org/10.1016/j.parco.2012.07.001openalex-snapshot
Graph coloring algorithms for multi-core and massively multithreaded architectures
inferredcites →https://doi.org/10.1016/j.parco.2015.03.003openalex-snapshot
Parallel heuristics for scalable community detection
inferredcites →https://doi.org/10.1016/j.physrep.2009.11.002openalex-snapshot
Community detection in graphs
inferredcites →https://doi.org/10.1016/j.tcs.2005.09.027openalex-snapshot
Equitable colorings of bounded treewidth graphs
inferredcites →https://doi.org/10.1038/30918openalex-snapshot
Collective dynamics of ‘small-world’ networks
inferredcites →https://doi.org/10.1038/nrg2857openalex-snapshot
Computational solutions to large-scale data management and analysis
inferredcites →https://doi.org/10.1073/pnas.0601602103openalex-snapshot
Modularity and community structure in networks
inferredcites →https://doi.org/10.1109/hipc.2014.7116708openalex-snapshot
Scaling graph community detection on the Tilera many-core architecture
inferredcites →https://doi.org/10.1109/hoti.2008.22openalex-snapshot
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
inferredcites →https://doi.org/10.1109/hpca.2013.6522344openalex-snapshot
Scaling towards kilo-core processors with asymmetric high-radix topologies
inferredcites →https://doi.org/10.1109/icnc.2011.6022061openalex-snapshot
A parallel computing model for large-graph mining with MapReduce
inferredcites →https://doi.org/10.1109/icpp.2005.55openalex-snapshot
On the Architectural Requirements for Efficient Execution of Graph Algorithms
inferredcites →https://doi.org/10.1109/icpp.2013.27openalex-snapshot
Engineering High-Performance Community Detection Heuristics for Massive Graphs
inferredcites →https://doi.org/10.1109/iitc.2005.1499949openalex-snapshot
Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures
inferredcites →https://doi.org/10.1109/ipdps.2015.113openalex-snapshot
Balanced Coloring for Parallel Computing Applications
inferredcites →https://doi.org/10.1109/isqed.2015.7085460openalex-snapshot
Enhancing performance of wireless NoCs with distributed MAC protocols
inferredcites →https://doi.org/10.1109/jetcas.2012.2193835openalex-snapshot
Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges
inferredcites →https://doi.org/10.1109/jetcas.2012.2193936openalex-snapshot
Swizzle-Switch Networks for Many-Core Systems
inferredcites →https://doi.org/10.1109/jssc.2007.900236openalex-snapshot
Communication Using Antennas Fabricated in Silicon Integrated Circuits
inferredcites →https://doi.org/10.1109/jstqe.2013.2295882openalex-snapshot
Design Challenges in Silicon Photonics
inferredcites →https://doi.org/10.1109/l-ca.2007.10openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferredcites →https://doi.org/10.1109/led.2004.841461openalex-snapshot
Wireless communication in a flip-chip package using integrated antennas on silicon substrates
inferredcites →https://doi.org/10.1109/mc.2013.260openalex-snapshot
Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks
inferredcites →https://doi.org/10.1109/mm.2008.18openalex-snapshot
Toward Ideal On-Chip Communication Using Express Virtual Channels
inferredcites →https://doi.org/10.1109/mm.2014.48openalex-snapshot
Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip
inferredcites →https://doi.org/10.1109/tap.2007.905867openalex-snapshot
Propagation Mechanisms of Radio Waves Over Intra-Chip Channels With Integrated Antennas: Frequency-Domain Measurements and Time-Domain Analysis
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tc.2012.224openalex-snapshot
Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects
inferredcites →https://doi.org/10.1109/tcad.2008.2010691openalex-snapshot
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
inferredcites →https://doi.org/10.1109/tcad.2014.2351577openalex-snapshot
Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing
inferredcites →https://doi.org/10.1109/tvlsi.2006.878263openalex-snapshot
"It's a small world after all": NoC performance optimization via long-range link insertion
inferredcites →https://doi.org/10.1137/1.9780898718003openalex-snapshot
Iterative Methods for Sparse Linear Systems
inferredcites →https://doi.org/10.1145/2063384openalex-snapshot
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
inferredcites →https://doi.org/10.1145/2535753.2535757openalex-snapshot
Analysis of computing and energy performance of multicore, NUMA, and manycore platforms for an irregular application
inferredcites →https://doi.org/10.48550/arxiv.cond-mat/0501420openalex-snapshot
Spatial small-world networks: A wiring-cost perspective
inferredcites →https://doi.org/10.6028/jres.084.024openalex-snapshot
A graph coloring algorithm for large scheduling problems
inferredcites →https://doi.org/10.7873/date.2014.110openalex-snapshot
Time-critical computing on a single-chip massively parallel processor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.6055openalex-snapshot
A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip
inferred← citeshttps://doi.org/10.1007/s11227-023-05208-0openalex-snapshot
Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC
inferred← citeshttps://doi.org/10.1109/bigdata.2016.7840780openalex-snapshot
An edge-set based large scale graph processing system
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00034openalex-snapshot
WiDir: A Wireless-Enabled Directory Cache Coherence Protocol
inferred← citeshttps://doi.org/10.1109/isqed48828.2020.9137000openalex-snapshot
Learning-Enabled NoC Design for Heterogeneous Manycore Systems
inferred← citeshttps://doi.org/10.1109/jsac.2024.3399253openalex-snapshot
Electromagnetic Nanonetworks Beyond 6G: From Wearable and Implantable Networks to On-Chip and Quantum Communication
inferred← citeshttps://doi.org/10.1109/tc.2017.2706278openalex-snapshot
A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis
inferred← citeshttps://doi.org/10.1109/tc.2017.2777863openalex-snapshot
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2748884openalex-snapshot
Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2843282openalex-snapshot
Scalable Network-on-Chip Architectures for Brain–Machine Interface Applications
inferred← citeshttps://doi.org/10.1145/3061639.3062194openalex-snapshot
Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC
inferred← citeshttps://doi.org/10.1145/3240765.3243480openalex-snapshot
Hybrid on-chip communication architectures for heterogeneous manycore systems
inferred← citeshttps://doi.org/10.1145/3482880openalex-snapshot
High-Performance and Energy-Efficient 3D Manycore GPU Architecture for Accelerating Graph Analytics
inferred← citeshttps://doi.org/10.1145/3514354openalex-snapshot
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations
inferred← citeshttps://doi.org/10.23919/date.2017.7927204openalex-snapshot
Performance evaluation and design trade-offs for wireless-enabled SMART NoC
inferred← citeshttps://doi.org/10.23919/date.2019.8715024openalex-snapshot
A Brief Survey of Algorithms, Architectures, and Challenges toward Extreme-scale Graph Analytics
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