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Main Memory in HPC
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/cpe.728openalex-snapshot
The LINPACK Benchmark: past, present and future
inferredcites →https://doi.org/10.1007/978-3-319-17248-4_9openalex-snapshot
Performance Modeling of the HPCG Benchmark
inferredcites →https://doi.org/10.1016/b978-0-12-809194-4.00002-8openalex-snapshot
Knights Landing overview
inferredcites →https://doi.org/10.1109/ccgrid.2007.92openalex-snapshot
Reducing Connection Memory Requirements of MPI for InfiniBand Clusters: A Message Coalescing Approach
inferredcites →https://doi.org/10.1109/hpca.2015.7056027openalex-snapshot
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories
inferredcites →https://doi.org/10.1109/iiswc.2006.302741openalex-snapshot
DFS: A Simple to Write Yet Difficult to Execute Benchmark
inferredcites →https://doi.org/10.1109/iiswc.2011.6114176openalex-snapshot
On the memory system requirements of future scientific applications: Four case-studies
inferredcites →https://doi.org/10.1109/ipdps.2011.24openalex-snapshot
Exploiting Data Similarity to Reduce Memory Footprints
inferredcites →https://doi.org/10.1109/mc.2015.338openalex-snapshot
The TOP500 List and Progress in High-Performance Computing
inferredcites →https://doi.org/10.1109/micro.2014.56openalex-snapshot
Transparent Hardware Management of Stacked DRAM as Part of Memory
inferredcites →https://doi.org/10.1109/micro.2014.63openalex-snapshot
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
inferredcites →https://doi.org/10.1109/mm.2016.25openalex-snapshot
Knights Landing: Second-Generation Intel Xeon Phi Product
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1109/sc.2014.82openalex-snapshot
Efficient Shared-Memory Implementation of High-Performance Conjugate Gradient Benchmark and its Application to Unstructured Matrices
inferredcites →https://doi.org/10.1145/1964218.1964230openalex-snapshot
Should we worry about memory loss?
inferredcites →https://doi.org/10.1145/2989081.2989083openalex-snapshot
Large-Memory Nodes for Energy Efficient High-Performance Computing
inferredcites →https://doi.org/10.1145/331532.331573openalex-snapshot
Architectural requirements and scalability of the NAS parallel benchmarks
inferredcites →https://doi.org/10.2172/1089988openalex-snapshot
Toward a New Metric for Ranking High Performance Computing Systems
inferredcites →https://doi.org/10.2172/1113870openalex-snapshot
HPCG Benchmark Technical Specification
inferredcites →https://doi.org/10.2172/1131028openalex-snapshot
Large Scale Computing and Storage Requirements for Fusion Energy Sciences: Target 2017
inferredcites →https://doi.org/10.2172/1169335openalex-snapshot
High Performance Computing and Storage Requirements for Nuclear Physics: Target 2017
inferredcites →https://doi.org/10.2172/1471098openalex-snapshot
Large Scale Computing and Storage Requirements for Basic Energy Sciences: Target 2017. Report of the NERSC Requirements Review Conducted October 8–9, 2013, Gathersburg, MD
inferredcites →https://doi.org/10.5555/2820282.2820333openalex-snapshot
Limpio: LIghtweight MPI instrumentatiOn
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-72971-8_13openalex-snapshot
A Survey of Application Memory Usage on a National Supercomputer: An Analysis of Memory Requirements on ARCHER
inferred← citeshttps://doi.org/10.1007/978-3-319-96983-1_10openalex-snapshot
HPC Benchmarking: Scaling Right and Looking Beyond the Average
inferred← citeshttps://doi.org/10.1007/s00366-023-01890-zopenalex-snapshot
General resource manager for computationally demanding scientific software (MARE)
inferred← citeshttps://doi.org/10.1007/s10586-021-03296-2openalex-snapshot
APR: adaptive page replacement scheme for scientific applications
inferred← citeshttps://doi.org/10.1109/access.2019.2954169openalex-snapshot
Survey of Memory Management Techniques for HPC and Cloud Computing
inferred← citeshttps://doi.org/10.1109/access.2021.3053162openalex-snapshot
Preemptive Parallel Job Scheduling for Heterogeneous Systems Supporting Urgent Computing
inferred← citeshttps://doi.org/10.1109/arith.2019.00028openalex-snapshot
Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor
inferred← citeshttps://doi.org/10.1109/asap54787.2022.00028openalex-snapshot
Design Space Exploration for Memory-Oriented Approximate Computing Techniques
inferred← citeshttps://doi.org/10.1109/cahpc.2018.8645891openalex-snapshot
Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned
inferred← citeshttps://doi.org/10.1109/cluster.2019.8891001openalex-snapshot
Learning from Five-year Resource-Utilization Data of Titan System
inferred← citeshttps://doi.org/10.1109/icetsis61505.2024.10459495openalex-snapshot
Exploring Approximate Memory for Energy-Efficient Computing
inferred← citeshttps://doi.org/10.1109/icpads53394.2021.00041openalex-snapshot
Improving HPC System Throughput and Response Time using Memory Disaggregation
inferred← citeshttps://doi.org/10.1109/impact53160.2021.9696848openalex-snapshot
Die-stacking Placement for Heterogeneous integration Architecture
inferred← citeshttps://doi.org/10.1109/ipdps57955.2024.00021openalex-snapshot
Software Resource Disaggregation for HPC with Serverless Computing
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00064openalex-snapshot
Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems
inferred← citeshttps://doi.org/10.1109/mcsoc67473.2025.00030openalex-snapshot
Hybrid Interconnect and Intermediate Memory-Based 2.5D NoC Architecture for High Performance Computing Applications
inferred← citeshttps://doi.org/10.1109/sbac-pad63648.2024.00022openalex-snapshot
Disaggregated Memory with SmartNIC Offloading: a Case Study on Graph Processing
inferred← citeshttps://doi.org/10.1109/sbac-pad63648.2024.00023openalex-snapshot
Analyzing HPC Monitoring Data With a View Towards Efficient Resource Utilization
inferred← citeshttps://doi.org/10.1109/sips50750.2020.9195262openalex-snapshot
Approximate Buffers for Reducing Memory Requirements: Case Study on SKA
inferred← citeshttps://doi.org/10.1145/3352460.3358267openalex-snapshot
Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support
inferred← citeshttps://doi.org/10.1145/3387902.3392625openalex-snapshot
Contention-aware application performance prediction for disaggregated memory systems
inferred← citeshttps://doi.org/10.1145/3422575.3422791openalex-snapshot
The Need for Precise and Efficient Memory Capacity Budgeting
inferred← citeshttps://doi.org/10.1145/3488423.3519336openalex-snapshot
A Holistic View of Memory Utilization on HPC Systems: Current and Future Trends
inferred← citeshttps://doi.org/10.1145/3514245openalex-snapshot
A Case For Intra-rack Resource Disaggregation in HPC
inferred← citeshttps://doi.org/10.1145/3589013.3596678openalex-snapshot
Accelerating Performance of GPU-based Workloads Using CXL
inferred← citeshttps://doi.org/10.1145/3624062.3624174openalex-snapshot
Dynamic Memory Provisioning on Disaggregated HPC Systems
inferred← citeshttps://doi.org/10.1145/3651154openalex-snapshot
Load Balancing with Job-Size Testing: Performance Improvement or Degradation?
inferred← citeshttps://doi.org/10.1145/3712285.3759797openalex-snapshot
C.A.T.S.: Memory and Control Flow Tracing for Whole-Program Performance Analysis
inferred← citeshttps://doi.org/10.1177/1094342018814593openalex-snapshot
Pricing schemes for energy-efficient HPC systems: Design and exploration
inferred← citeshttps://doi.org/10.1177/1094342019847264openalex-snapshot
Implementing efficient data compression and encryption in a persistent key-value store for HPC
inferred← citeshttps://doi.org/10.14529/jsfi200104openalex-snapshot
Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems
inferred← citeshttps://doi.org/10.3389/fninf.2022.883742openalex-snapshot
STEPS 4.0: Fast and memory-efficient molecular simulations of neurons at the nanoscale
inferred← citeshttps://doi.org/10.3390/chemengineering5020021openalex-snapshot
Fortran Coarray Implementation of Semi-Lagrangian Convected Air Particles within an Atmospheric Model
inferred← citeshttps://doi.org/10.4218/etrij.2020-0393openalex-snapshot
Multi‐communication layered HPL model and its application to GPU clusters
inferred← citeshttps://doi.org/10.5821/dissertation-2117-121194openalex-snapshot
Memory systems for high-performance computing: the capacity and reliability implications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-134613openalex-snapshot
Memory bandwidth and latency in HPC: system requirements and performance impact
inferred← citeshttps://doi.org/10.5821/dissertation-2117-183884openalex-snapshot
Virtualization techniques for memory resource exploitation
inferred← citeshttps://doi.org/10.5821/dissertation-2117-363908openalex-snapshot
HPC memory systems: Implications of system simulation and checkpointing
inferred← citeshttps://doi.org/10.5821/dissertation-2117-404651openalex-snapshot
Job scheduling for disaggregated memory in high performance computing systems
inferred← citeshttps://doi.org/10.70675/8fb8221cz0538z498bzb56dz9ee0dda3d113openalex-snapshot
Approximated Computing-based Methods for Hardware Resources Reduction Targeting Heterogeneous Systems
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