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Hoplite
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/fccm.2006.55openalex-snapshot
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
inferredcites →https://doi.org/10.1109/fccm.2016.12openalex-snapshot
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator
inferredcites →https://doi.org/10.1109/fpl.2015.7293956openalex-snapshot
Hoplite: Building austere overlay NoCs for FPGAs
inferredcites →https://doi.org/10.1109/fpt.2012.6412110openalex-snapshot
FPGA optimized packet-switched NoC using split and merge primitives
inferredcites →https://doi.org/10.1109/fpt.2012.6412118openalex-snapshot
Design tradeoffs for hard and soft FPGA-based Networks-on-Chip
inferredcites →https://doi.org/10.1109/isqed.2006.2openalex-snapshot
Proceedings of the 2006 7th International Symposium on Quality Electronic Design
inferredcites →https://doi.org/10.1109/isqed.2015.7085472openalex-snapshot
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks
inferredcites →https://doi.org/10.1109/nocs.2010.10openalex-snapshot
Evaluating Bufferless Flow Control for On-chip Networks
inferredcites →https://doi.org/10.1109/nocs.2012.19openalex-snapshot
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers
inferredcites →https://doi.org/10.1109/nocs.2012.8openalex-snapshot
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
inferredcites →https://doi.org/10.1109/reconfig.2014.7032481openalex-snapshot
Keynote 3 — The past and future of FPGA soft processors
inferredcites →https://doi.org/10.1109/t-c.1971.223159openalex-snapshot
On a Pin Versus Block Relationship For Partitions of Logic Graphs
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1555815.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669145openalex-snapshot
Low-cost router microarchitecture for on-chip networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-80629-2_11openalex-snapshot
Conclusions and Future Work
inferred← citeshttps://doi.org/10.1007/978-3-031-80629-2_9openalex-snapshot
Time-Domain-Multiplexed Interconnect
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_49-1openalex-snapshot
Field-Programmable Gate Array Architecture
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_49openalex-snapshot
Field-Programmable Gate Array Architecture
inferred← citeshttps://doi.org/10.1007/s11227-021-03850-0openalex-snapshot
Optimal port allocation scheme for deflection-routed networks-on-chip
inferred← citeshttps://doi.org/10.1007/s11265-021-01640-8openalex-snapshot
The TaPaSCo Open-Source Toolflow
inferred← citeshttps://doi.org/10.1016/j.mejo.2018.08.013openalex-snapshot
Dual Split-Merge: A high throughput router architecture for FPGAs
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.06.005openalex-snapshot
Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources
inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.06.009openalex-snapshot
Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC
inferred← citeshttps://doi.org/10.1088/1742-6596/1746/1/012072openalex-snapshot
Performance Analysis of Arbitration Scheduling Algorithm Based on RR Optimization for Network-on-chips
inferred← citeshttps://doi.org/10.1109/fccm.2018.00027openalex-snapshot
LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786203openalex-snapshot
Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs
inferred← citeshttps://doi.org/10.1109/fpl.2019.00020openalex-snapshot
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00015openalex-snapshot
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00031openalex-snapshot
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00026openalex-snapshot
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
inferred← citeshttps://doi.org/10.1109/icfpt51103.2020.00035openalex-snapshot
Fast Linking of Separately-Compiled FPGA Blocks without a NoC
inferred← citeshttps://doi.org/10.1109/ipdpsw50202.2020.00025openalex-snapshot
SpiderWeb - High Performance FPGA NoC
inferred← citeshttps://doi.org/10.1109/isca.2018.00067openalex-snapshot
FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs
inferred← citeshttps://doi.org/10.1109/mcas.2021.3071607openalex-snapshot
FPGA Architecture: Principles and Progression
inferred← citeshttps://doi.org/10.1109/mcsoc67473.2025.00054openalex-snapshot
Toward Predictable Deflection Routing in Routerless NoCs for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/nocarc51382.2020.9234580openalex-snapshot
Run-time Reconfiguration of NoC in Xilinx ACAP Architecture
inferred← citeshttps://doi.org/10.1109/tc.2022.3214113openalex-snapshot
Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012748openalex-snapshot
HopliteRT: Real-Time NoC for FPGA
inferred← citeshttps://doi.org/10.1145/3373087.3375309openalex-snapshot
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs
inferred← citeshttps://doi.org/10.1145/3507699openalex-snapshot
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators
inferred← citeshttps://doi.org/10.1145/3547657openalex-snapshot
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA
inferred← citeshttps://doi.org/10.1145/3593025openalex-snapshot
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration
inferred← citeshttps://doi.org/10.1145/3623278.3624750openalex-snapshot
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
inferred← citeshttps://doi.org/10.1145/3626202.3637579openalex-snapshot
A 475 MHz Manycore FPGA Accelerator for RTL Simulation
inferred← citeshttps://doi.org/10.1145/3677035openalex-snapshot
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators
inferred← citeshttps://doi.org/10.1145/3762650openalex-snapshot
Developing Deadlock-Free Routing Algorithms in Torus NoC: A Formal Approach
inferred← citeshttps://doi.org/10.1145/3779449openalex-snapshot
OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs
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