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Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels

https://doi.org/10.1145/3177965
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1063/1.3653279openalex-snapshot
Non-resistance-based cell-state metric for phase-change memory
inferredcites →https://doi.org/10.1109/asscc.2014.7008879openalex-snapshot
A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory
inferredcites →https://doi.org/10.1109/cluster.2017.130openalex-snapshot
Utility-Based Hybrid Memory Management
inferredcites →https://doi.org/10.1109/clustr.2000openalex-snapshot
Proceedings IEEE International Conference on Cluster Computing. CLUSTER 2000
inferredcites →https://doi.org/10.1109/dsn.2014.31openalex-snapshot
A Reliable 3D MLC PCM Architecture with Resistance Drift Predictor
inferredcites →https://doi.org/10.1109/dsn.2015.49openalex-snapshot
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery
inferredcites →https://doi.org/10.1109/dsn.2016.27openalex-snapshot
ReadDuo: Constructing Reliable MLC Phase Change Memory through Fast and Robust Readout
inferredcites →https://doi.org/10.1109/hpca.2010.5416645openalex-snapshot
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
inferredcites →https://doi.org/10.1109/hpca.2011.5749716openalex-snapshot
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
inferredcites →https://doi.org/10.1109/hpca.2012.6169027openalex-snapshot
Improving write operations in MLC phase change memory
inferredcites →https://doi.org/10.1109/hpca.2015.7056042openalex-snapshot
Reducing read latency of phase change memory via early read and Turbo Read
inferredcites →https://doi.org/10.1109/hpca.2015.7056062openalex-snapshot
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery
inferredcites →https://doi.org/10.1109/hpca.2017.61openalex-snapshot
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques
inferredcites →https://doi.org/10.1109/hpca34535.2015openalex-snapshot
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)
inferredcites →https://doi.org/10.1109/iccd.2011.6081394openalex-snapshot
Energy-efficient multi-level cell phase-change memory system with data encoding
inferredcites →https://doi.org/10.1109/iccd.2012.6378623openalex-snapshot
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
inferredcites →https://doi.org/10.1109/iccd.2013.6657034openalex-snapshot
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation
inferredcites →https://doi.org/10.1109/iedm.1994.383476openalex-snapshot
Proceedings of 1994 IEEE International Electron Devices Meeting
inferredcites →https://doi.org/10.1109/iedm.2007.4418973openalex-snapshot
Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory
inferredcites →https://doi.org/10.1109/iedm.2011.6131482openalex-snapshot
Drift-resilient cell-state metric for multilevel phase-change memory
inferredcites →https://doi.org/10.1109/isca.2004.1310750openalex-snapshot
Proceedings. 31st Annual International Symposium on Computer Architecture
inferredcites →https://doi.org/10.1109/isca.2016.52openalex-snapshot
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs
inferredcites →https://doi.org/10.1109/isca.2016.66openalex-snapshot
Boosting Access Parallelism to PCM-Based Main Memory
inferredcites →https://doi.org/10.1109/iscas.2004.1328657openalex-snapshot
Proceedings of 2004 IEEE International Symposium on Circuits and Systems
inferredcites →https://doi.org/10.1109/iscas.2007.377981openalex-snapshot
A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/isqed.2010.5450549openalex-snapshot
Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory
inferredcites →https://doi.org/10.1109/jproc.2017.2713127openalex-snapshot
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives
inferredcites →https://doi.org/10.1109/jsac.2016.2603608openalex-snapshot
Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory
inferredcites →https://doi.org/10.1109/jssc.2008.2007152openalex-snapshot
A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology
inferredcites →https://doi.org/10.1109/jssc.2008.917558openalex-snapshot
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories
inferredcites →https://doi.org/10.1109/mc.2003.1250880openalex-snapshot
Energy management for commercial servers
inferredcites →https://doi.org/10.1109/micro.2010.46openalex-snapshot
SAFER: Stuck-At-Fault Error Recovery for Memories
inferredcites →https://doi.org/10.1109/ted.2006.888752openalex-snapshot
Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories
inferredcites →https://doi.org/10.1109/tvlsi.2014.2363102openalex-snapshot
Variable Resistance Spectrum Assignment in Phase Change Memory Systems
inferredcites →https://doi.org/10.1109/vlsit.2008.4588577openalex-snapshot
Two-bit cell operation in diode-switch phase change memory cells with 90nm technology
inferredcites →https://doi.org/10.1109/vlsit.2010.5556227openalex-snapshot
MLC PRAM with SLC write-speed and robust read scheme
inferredcites →https://doi.org/10.1145/1028176.1006719openalex-snapshot
Adaptive Cache Compression for High-Performance Processors
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1669112.1669118openalex-snapshot
Characterizing flash memory
inferredcites →https://doi.org/10.1145/1735970.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1736020.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1815961.1815980openalex-snapshot
Use ECP, not ECC, for hard failures in resistive memories
inferredcites →https://doi.org/10.1145/1815961.1815981openalex-snapshot
Morphable memory system
inferredcites →https://doi.org/10.1145/1815961.1816014openalex-snapshot
Security refresh
inferredcites →https://doi.org/10.1145/2086696.2086732openalex-snapshot
Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems
inferredcites →https://doi.org/10.1145/2155620.2155658openalex-snapshot
Pay-As-You-Go
inferredcites →https://doi.org/10.1145/2429384.2429498openalex-snapshot
Multi-level cell STT-RAM
inferredcites →https://doi.org/10.1145/2485922.2485959openalex-snapshot
Bit mapping for balanced PCM cell programming
inferredcites →https://doi.org/10.1145/2485922.2485960openalex-snapshot
Tri-level-cell phase change memory
inferredcites →https://doi.org/10.1145/2540708.2540712openalex-snapshot
Approximate storage in solid-state memories
inferredcites →https://doi.org/10.1145/2540708.2540745openalex-snapshot
Aegis
inferredcites →https://doi.org/10.1145/2541228.2555307openalex-snapshot
WADE
inferredcites →https://doi.org/10.1145/2591971.2591994openalex-snapshot
Neighbor-cell assisted error correction for MLC NAND flash memories
inferredcites →https://doi.org/10.1145/2637364.2591994openalex-snapshot
Neighbor-cell assisted error correction for MLC NAND flash memories
inferredcites →https://doi.org/10.1145/2669365openalex-snapshot
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories
inferredcites →https://doi.org/10.1145/2678373.2665731openalex-snapshot
A low power and reliable charge pump design for phase change memories
inferredcites →https://doi.org/10.1145/2764905openalex-snapshot
Architecting the Last-Level Cache for GPUs using STT-RAM Technology
inferredcites →https://doi.org/10.1145/2820610openalex-snapshot
Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM
inferredcites →https://doi.org/10.1145/2829951openalex-snapshot
SPCM
inferredcites →https://doi.org/10.1145/3007787.3001192openalex-snapshot
Mellow writes
inferredcites →https://doi.org/10.1145/3007787.3001211openalex-snapshot
Boosting access parallelism to PCM-based main memory
inferredcites →https://doi.org/10.1145/3037697.3037706openalex-snapshot
Thermostat
inferredcites →https://doi.org/10.1145/774572openalex-snapshot
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design - ICCAD '02
inferredcites →https://doi.org/10.1145/800015openalex-snapshot
Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s44275-024-00023-yopenalex-snapshot
Phase change memory programming circuit with improved speed
inferred← citeshttps://doi.org/10.1016/bs.adcom.2019.09.001openalex-snapshot
Introduction to non-volatile memory technologies
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Phase-change memory architectures
inferred← citeshttps://doi.org/10.1016/j.future.2020.01.013openalex-snapshot
Pattern analysis based data management method and memory-disk integrated system for high performance computing
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.103008openalex-snapshot
A survey on techniques for improving Phase Change Memory (PCM) lifetime
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TTEC: Data Allocation Optimization for Morphable Scratchpad Memory in Embedded Systems
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FETs for Analog Neural MACs
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ML-SECure: Machine Learning-Based Soft Error Correction Pipeline for Multi-Level Cell PCM
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Harmonica: Hybrid Accelerator to Overcome Imperfections of Mixed-signal DNN Accelerators
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Risk-5: Controlled Approximations for RISC-V
inferred← citeshttps://doi.org/10.1109/tcad.2022.3210068openalex-snapshot
eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory
inferred← citeshttps://doi.org/10.1109/tdmr.2021.3087807openalex-snapshot
Exploiting Resistance Drift Characteristics to Improve Reliability of LDPC-Assisted Phase-Change Memory
inferred← citeshttps://doi.org/10.1145/3177876openalex-snapshot
Express Read in MLC Phase Change Memories
inferred← citeshttps://doi.org/10.1145/3289187openalex-snapshot
Reducing Writebacks Through In-Cache Displacement
inferred← citeshttps://doi.org/10.1145/3332257openalex-snapshot
A Survey on PCM Lifetime Enhancement Schemes
inferred← citeshttps://doi.org/10.31763/aet.v2i2.1006openalex-snapshot
Implementation of a new coding scheme for improving the SET operations in Phase Change Memory (PCM)
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NVM Storage in IoT Devices: Opportunities and Challenges
inferred← citeshttps://doi.org/10.3390/electronics9040626openalex-snapshot
Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory
inferred← citeshttps://doi.org/10.47749/t/unicamp.2022.1238495openalex-snapshot
Software and hardware interfaces for approximate memories
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Storage Class Memory: Principles, Problems, and Possibilities
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A Survey on Recent Hardware Data Prefetching Approaches with An Emphasis on Servers
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