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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.sse.2012.06.003openalex-snapshot
Modified write-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe
inferredcites →https://doi.org/10.1063/1.1598272openalex-snapshot
One-dimensional heat conduction model for an electrical phase change random access memory device with an 8F2 memory cell (F=0.15 μm)
inferredcites →https://doi.org/10.1109/2.976918openalex-snapshot
2001 technology roadmap for semiconductors
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/aspdac.2011.5722206openalex-snapshot
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage
inferredcites →https://doi.org/10.1109/dsn.2011.5958219openalex-snapshot
Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system
inferredcites →https://doi.org/10.1109/hpca.2010.5416645openalex-snapshot
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
inferredcites →https://doi.org/10.1109/hpca.2011.5749742openalex-snapshot
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system
inferredcites →https://doi.org/10.1109/hpca.2011.5749752openalex-snapshot
FREE-p: Protecting non-volatile memory against both hard and soft errors
inferredcites →https://doi.org/10.1109/hpca.2012.6169027openalex-snapshot
Improving write operations in MLC phase change memory
inferredcites →https://doi.org/10.1109/hpca.2015.7056042openalex-snapshot
Reducing read latency of phase change memory via early read and Turbo Read
inferredcites →https://doi.org/10.1109/iedm.2007.4418973openalex-snapshot
Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory
inferredcites →https://doi.org/10.1109/isscc.2012.6176872openalex-snapshot
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
inferredcites →https://doi.org/10.1109/jssc.2008.2006439openalex-snapshot
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2010.22openalex-snapshot
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
inferredcites →https://doi.org/10.1109/micro.2010.46openalex-snapshot
SAFER: Stuck-At-Fault Error Recovery for Memories
inferredcites →https://doi.org/10.1109/micro.2012.10openalex-snapshot
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
inferredcites →https://doi.org/10.1109/pact.2011.71openalex-snapshot
Memory Architecture for Integrating Emerging Memory Technologies
inferredcites →https://doi.org/10.1109/tcsi.2012.2220459openalex-snapshot
A 256-Mcell Phase-Change Memory Chip Operating at $2{+}$ Bit/Cell
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1669112.1669116openalex-snapshot
Characterizing and mitigating the impact of process variations on phase change based memory systems
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1815961.1815980openalex-snapshot
Use ECP, not ECC, for hard failures in resistive memories
inferredcites →https://doi.org/10.1145/2155620.2155642openalex-snapshot
Preventing PCM banks from seizing too much power
inferredcites →https://doi.org/10.1145/2228360.2228521openalex-snapshot
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
inferredcites →https://doi.org/10.1145/2485922.2485955openalex-snapshot
Reducing memory access latency with asymmetric DRAM bank organizations
inferredcites →https://doi.org/10.1145/2508148.2485955openalex-snapshot
Reducing memory access latency with asymmetric DRAM bank organizations
inferredcites →https://doi.org/10.1145/2669365openalex-snapshot
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories
inferredcites →https://doi.org/10.1184/r1/6469397openalex-snapshot
Techniques for Data Mapping and Buffering to Exploit Asymmetry in Multi-Level Cell (Phase Change) Memory
inferredcites →https://doi.org/10.1557/mrs2004.236openalex-snapshot
Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology
inferredcites →https://doi.org/10.5555/1950815.1950821openalex-snapshot
AdaMS: adaptive MLC/SLC phase-change memory design for file storage
inferredcites →https://doi.org/10.5555/2208461.2208463openalex-snapshot
The bleak future of NAND flash memory
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-018-2466-7openalex-snapshot
Adaptive correlated prefetch with large-scale hybrid memory system for stream processing
inferred← citeshttps://doi.org/10.1016/bs.adcom.2019.09.001openalex-snapshot
Introduction to non-volatile memory technologies
inferred← citeshttps://doi.org/10.1016/bs.adcom.2019.10.002openalex-snapshot
Inter-line level schemes for handling hard errors in PCMs
inferred← citeshttps://doi.org/10.1109/islped.2017.8009204openalex-snapshot
Efficient query processing in crossbar memory
inferred← citeshttps://doi.org/10.1109/lca.2017.2756051openalex-snapshot
Flow-Based Simulation Methodology
inferred← citeshttps://doi.org/10.1109/pccc.2017.8280431openalex-snapshot
H-NVMe: A hybrid framework of NVMe-based storage system in cloud computing environment
inferred← citeshttps://doi.org/10.1145/3177965openalex-snapshot
Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels
inferred← citeshttps://doi.org/10.1155/2022/9552517openalex-snapshot
PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping
inferred← citeshttps://doi.org/10.48550/arxiv.1904.11560openalex-snapshot
A Survey on Tiering and Caching in High-Performance Storage Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1909.12221openalex-snapshot
Storage Class Memory: Principles, Problems, and Possibilities
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