On the public citation graph
DDRNoC
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2009.4798251openalex-snapshot
Express Cube Topologies for on-Chip Interconnects
inferredcites →https://doi.org/10.1109/icecs.2016.7841140openalex-snapshot
RapidLink: A network-on-chip architecture with double-data-rate links
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/isscc.2008.4523070openalex-snapshot
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
inferredcites →https://doi.org/10.1109/jetcas.2012.2193936openalex-snapshot
Swizzle-Switch Networks for Many-Core Systems
inferredcites →https://doi.org/10.1109/jssc.2011.2108121openalex-snapshot
A 2 Tb/s 6 $\,\times\,$ 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
inferredcites →https://doi.org/10.1109/micro.2012.25openalex-snapshot
NOC-Out: Microarchitecting a Scale-Out Processor
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2007.4378783openalex-snapshot
A 5-GHz Mesh Interconnect for a Teraflops Processor
inferredcites →https://doi.org/10.1109/mm.2009.40openalex-snapshot
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
inferredcites →https://doi.org/10.1109/nocs.2010.25openalex-snapshot
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip
inferredcites →https://doi.org/10.1109/nocs.2010.26openalex-snapshot
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
inferredcites →https://doi.org/10.1109/nocs.2014.7008753openalex-snapshot
High-performance energy-efficient NoC fabrics: Evolution and future challenges
inferredcites →https://doi.org/10.1109/oic.2013.6552941openalex-snapshot
How to stop interconnects from hindering the future of computing!
inferredcites →https://doi.org/10.1109/tc.2016.2519916openalex-snapshot
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing
inferredcites →https://doi.org/10.1109/tcsi.2017.2734689openalex-snapshot
Networks-on-Chip With Double-Data-Rate Links
inferredcites →https://doi.org/10.1109/vlsic.1994openalex-snapshot
Proceedings of 1994 IEEE Symposium on VLSI Circuits
inferredcites →https://doi.org/10.1109/vlsic.2007.4342758openalex-snapshot
A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
inferredcites →https://doi.org/10.1145/1065579.1065726openalex-snapshot
A low latency router supporting adaptivity for on-chip interconnects
inferredcites →https://doi.org/10.1145/1183401.1183430openalex-snapshot
Design tradeoffs for tiled CMP on-chip networks
inferredcites →https://doi.org/10.1145/1654059.1654112openalex-snapshot
Allocator implementations for network-on-chip routers
inferredcites →https://doi.org/10.1145/1669112.1669151openalex-snapshot
A case for dynamic frequency tuning in on-chip networks
inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-021-04098-4openalex-snapshot
Power efficient network selector placement in control plane of multiple networks-on-chip
inferred← citeshttps://doi.org/10.1016/j.jpdc.2020.09.013openalex-snapshot
Performance analysis of network-on-chip in many-core processors
inferred← citeshttps://doi.org/10.1016/j.mejo.2020.104947openalex-snapshot
A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock
inferred← citeshttps://doi.org/10.1109/apccas67402.2025.11377319openalex-snapshot
VitalSystem: A FauIt-Tolerant System Architecture for Wafer-Scale Integration
inferred← citeshttps://doi.org/10.1109/asap52443.2021.00043openalex-snapshot
Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00075openalex-snapshot
FastTrackNoC: A NoC with FastTrack Router Datapaths
inferred← citeshttps://doi.org/10.1109/ispass61541.2024.00025openalex-snapshot
BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling
inferred← citeshttps://doi.org/10.1109/mdat.2022.3202996openalex-snapshot
SynFull-RTL: Evaluation Methodology for RTL NoC Designs
inferred← citeshttps://doi.org/10.1109/nocs.2018.8512160openalex-snapshot
FreewayNoC: A DDR NoC with Pipeline Bypassing
inferred← citeshttps://doi.org/10.1109/tasc.2023.3236248openalex-snapshot
PaST-NoC: A Packet-Switched Superconducting Temporal NoC
inferred← citeshttps://doi.org/10.1109/tnet.2020.3034581openalex-snapshot
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers
inferred← citeshttps://doi.org/10.48550/arxiv.2006.12274openalex-snapshot
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect
inferred← citeshttps://doi.org/10.5555/3306619.3306627openalex-snapshot
FreewayNoC: a DDR NoC with pipeline bypassing
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