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NOC-Out: Microarchitecting a Scale-Out Processor
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/date.2009.5090700openalex-snapshot
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
inferredcites →https://doi.org/10.1109/hpca.2009.4798250openalex-snapshot
Elastic-buffer flow control for on-chip networks
inferredcites →https://doi.org/10.1109/micro.2003.1253187openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/micro.2007.29openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
inferredcites →https://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
inferredcites →https://doi.org/10.1109/mm.2006.79openalex-snapshot
SimFlex: Statistical Sampling of Computer System Simulation
inferredcites →https://doi.org/10.1109/mm.2012.71openalex-snapshot
Optimizing Data-Center TCO with Scale-Out Processors
inferredcites →https://doi.org/10.1109/nocs.2012.15openalex-snapshot
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1183401.1183430openalex-snapshot
Design tradeoffs for tiled CMP on-chip networks
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669145openalex-snapshot
Low-cost router microarchitecture for on-chip networks
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Traffic Patterns in Networks-on-Chip: A Survey
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NOC characteristics of cloud applications
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Performance analysis of the memory management unit under scale-out workloads
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BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling
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NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
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