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High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
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Man vs. computer: Benchmarking machine learning algorithms for traffic sign recognition
inferredcites →https://doi.org/10.1109/5.726791openalex-snapshot
Gradient-based learning applied to document recognition
inferredcites →https://doi.org/10.1109/fpl.2014.6927468openalex-snapshot
Pipelined compressor tree optimization using integer linear programming
inferredcites →https://doi.org/10.1109/icassp.2016.7471828openalex-snapshot
FPGA based implementation of deep neural networks using on-chip memory only
inferredcites →https://doi.org/10.1109/ijcnn.2003.1223944openalex-snapshot
Proceedings Of The International Joint Conference On Neural Networks 2003
inferredcites →https://doi.org/10.1109/ijcnn.2017.7966166openalex-snapshot
Ternary neural networks for resource-efficient AI applications
inferredcites →https://doi.org/10.1109/isca.2016.30openalex-snapshot
EIE: Efficient Inference Engine on Compressed Deep Neural Network
inferredcites →https://doi.org/10.1109/isscc.2017.7870349openalex-snapshot
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems
inferredcites →https://doi.org/10.1109/mdat.2016.2573586openalex-snapshot
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era
inferredcites →https://doi.org/10.1109/sips.2014.6986082openalex-snapshot
Fixed-point feedforward deep neural network design using weights +1, 0, and −1
inferredcites →https://doi.org/10.1109/tcad.2017.2682138openalex-snapshot
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
inferredcites →https://doi.org/10.1145/1815961.1816008openalex-snapshot
The rebirth of neural networks
inferredcites →https://doi.org/10.1145/3020078.3021740openalex-snapshot
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?
inferredcites →https://doi.org/10.1145/3020078.3021741openalex-snapshot
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
inferredcites →https://doi.org/10.1145/3020078.3021786openalex-snapshot
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)
inferredcites →https://doi.org/10.1145/3029580.3029586openalex-snapshot
Scaling Binarized Neural Networks on Reconfigurable Logic
inferredcites →https://doi.org/10.1145/3079758openalex-snapshot
Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1609/aaai.v31i1.11231openalex-snapshot
Inception-v4, Inception-ResNet and the Impact of Residual Connections on Learning
inferredcites →https://doi.org/10.2307/2317055openalex-snapshot
The Art of Computer Programming. Volume 2: Seminumerical Algorithms.
inferredcites →https://doi.org/10.23919/date.2017.7927222openalex-snapshot
A novel zero weight/activation-aware hardware architecture of convolutional neural network
inferredcites →https://doi.org/10.23919/fpl.2017.8056794openalex-snapshot
A high-throughput reconfigurable processing array for neural networks
inferredcites →https://doi.org/10.23919/fpl.2017.8056823openalex-snapshot
High performance binary neural networks on the Xeon+FPGA™ platform
inferredcites →https://doi.org/10.23919/fpl.2017.8056850openalex-snapshot
Scalable high-performance architecture for convolutional ternary neural networks on FPGA
inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot
Very Deep Convolutional Networks for Large-Scale Image Recognition
inferredcites →https://doi.org/10.48550/arxiv.1511.00363openalex-snapshot
BinaryConnect: Training Deep Neural Networks with binary weights during propagations
inferredcites →https://doi.org/10.48550/arxiv.1609.07061openalex-snapshot
Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations
inferredcites →https://doi.org/10.48550/arxiv.1611.01600openalex-snapshot
Loss-aware Binarization of Deep Networks
inferredcites →https://doi.org/10.48550/arxiv.1612.01064openalex-snapshot
Trained Ternary Quantization
inferredcites →https://doi.org/10.57702/e7wwo0zkopenalex-snapshot
Reading digits in natural images with unsupervised feature learning
inferredcites →https://doi.org/10.57702/zp44cu3gopenalex-snapshot
Learning Multiple Layers of Features from Tiny Images
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Arithmetic for Deep Learning
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inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102906openalex-snapshot
Area and power efficient pipelined hybrid merged adders for customized deep learning framework for FPGA implementation
inferred← citeshttps://doi.org/10.1016/j.micpro.2021.104039openalex-snapshot
TileNET: Hardware accelerator for ternary Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1039/d5nh00720hopenalex-snapshot
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inferred← citeshttps://doi.org/10.1088/1742-6596/1487/1/012028openalex-snapshot
Optimization of Energy Efficiency for FPGA-Based Convolutional Neural Networks Accelerator
inferred← citeshttps://doi.org/10.1109/dsd51259.2020.00057openalex-snapshot
Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems
inferred← citeshttps://doi.org/10.1109/eepe-tia67875.2025.11434198openalex-snapshot
Design and Implementation of a Serial-Parallel Collaborative Nano-Relay for Phase Voltage Difference-Based Single-Phase Ground Fault Detection in Distribution Networks
inferred← citeshttps://doi.org/10.1109/fccm48280.2020.00010openalex-snapshot
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00027openalex-snapshot
unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation
inferred← citeshttps://doi.org/10.1109/ijcnn54540.2023.10191784openalex-snapshot
Quantization Modes for Neural Network Inference: ASIC Implementation Trade-offs
inferred← citeshttps://doi.org/10.1109/jssc.2018.2881913openalex-snapshot
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width
inferred← citeshttps://doi.org/10.1109/tcsi.2020.3011984openalex-snapshot
A Partially Binarized Hybrid Neural Network System for Low-Power and Resource Constrained Human Activity Recognition
inferred← citeshttps://doi.org/10.1109/tvlsi.2019.2906678openalex-snapshot
Efficient Decompression of Binary Encoded Balanced Ternary Sequences
inferred← citeshttps://doi.org/10.1145/3374587.3374641openalex-snapshot
Research on the Current Status of Sparse Neural Network Acceleration Processing Technology in Deep Learning
inferred← citeshttps://doi.org/10.1145/3546182openalex-snapshot
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units
inferred← citeshttps://doi.org/10.1145/3611673openalex-snapshot
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation
inferred← citeshttps://doi.org/10.1145/3645097openalex-snapshot
High-efficiency Compressor Trees for Latest AMD FPGAs
inferred← citeshttps://doi.org/10.1145/3801487.3801837openalex-snapshot
Network Folding for Resource-Efficient Implementation of Stream-Dataflow Deep Neural Network Inference on FPGAs
inferred← citeshttps://doi.org/10.1201/9781003478713openalex-snapshot
Advancing Edge Artificial Intelligence
inferred← citeshttps://doi.org/10.1201/9781003478713-4openalex-snapshot
Inside the AI Accelerators: From High Performance to Energy Efficiency
inferred← citeshttps://doi.org/10.13052/rp-9788770041010openalex-snapshot
Advancing Edge Artificial Intelligence
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539457openalex-snapshot
SSR: Sparse Segment Reduction for Ternary GEMM Acceleration
inferred← citeshttps://doi.org/10.3390/electronics8060661openalex-snapshot
A Review of Binarized Neural Networks
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