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High-efficiency Compressor Trees for Latest AMD FPGAs

https://doi.org/10.1145/3645097
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-46493-0_32openalex-snapshot
XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
inferredcites →https://doi.org/10.1088/1748-0221/13/07/p07027openalex-snapshot
Fast inference of deep neural networks in FPGAs for particle physics
inferredcites →https://doi.org/10.1109/access.2019.2941985openalex-snapshot
Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters
inferredcites →https://doi.org/10.1109/aspdac.2008.4483927openalex-snapshot
Efficient synthesis of compressor trees on FPGAs
inferredcites →https://doi.org/10.1109/aspdac.2012.6165057openalex-snapshot
Selective time borrowing for DSP pipelines with hybrid voltage control loop
inferredcites →https://doi.org/10.1109/fpl.2009.5272301openalex-snapshot
Exploiting fast carry-chains of FPGAs for designing compressor trees
inferredcites →https://doi.org/10.1109/fpl.2013.6645544openalex-snapshot
Arithmetic core generation using bit heaps
inferredcites →https://doi.org/10.1109/fpl.2014.6927468openalex-snapshot
Pipelined compressor tree optimization using integer linear programming
inferredcites →https://doi.org/10.1109/icpads51040.2020.00026openalex-snapshot
XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices
inferredcites →https://doi.org/10.1109/pgec.1964.263830openalex-snapshot
A Suggestion for a Fast Multiplier
inferredcites →https://doi.org/10.1109/tc.2018.2795611openalex-snapshot
Advanced Compressor Tree Synthesis for FPGAs
inferredcites →https://doi.org/10.1109/tc.2023.3238128openalex-snapshot
Towards Globally Optimal Design of Multipliers for FPGAs
inferredcites →https://doi.org/10.1145/2068716.2068725openalex-snapshot
Compressor tree synthesis on commercial high-performance FPGAs
inferredcites →https://doi.org/10.1145/2228360.2228584openalex-snapshot
Chisel
inferredcites →https://doi.org/10.1145/2684746openalex-snapshot
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
inferredcites →https://doi.org/10.1145/3242897openalex-snapshot
FINN- R
inferredcites →https://doi.org/10.1145/3270764openalex-snapshot
High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression
inferredcites →https://doi.org/10.1145/3337929openalex-snapshot
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing
inferredcites →https://doi.org/10.1145/3506713openalex-snapshot
The Future of FPGA Acceleration in Datacenters and the Cloud
inferredcites →https://doi.org/10.1145/3546182openalex-snapshot
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units
inferredcites →https://doi.org/10.23919/fpl.2017.8056834openalex-snapshot
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
inferredcites →https://doi.org/10.48550/arxiv.2303.17951openalex-snapshot
FP8 versus INT8 for efficient deep learning inference
inferredcites →https://doi.org/10.52202/068431-1970openalex-snapshot
ZeroQuant: Efficient and Affordable Post-Training Quantization for Large-Scale Transformers
inferredcites →https://doi.org/10.5281/zenodo.5680908openalex-snapshot
fastmachinelearning/hls4ml: coris

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/tcad.2024.3511343zenodo-depositor-declared
Parallel Accurate Minifloat MACCs for Neural Network Inference on Versal FPGAs
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00016openalex-snapshot
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
inferred← citeshttps://doi.org/10.1109/tc.2025.3605766openalex-snapshot
Competition-Style Sorting Networks (CSN): A Framework for Hardware-Based Sorting Operations
inferred← citeshttps://doi.org/10.1142/s0218126626501835openalex-snapshot
Edge-AI-Assisted Real-Time Dynamic Anaglyph 3D Image Synthesis Using Hybrid VLSI Architecture with Adaptive Depth Estimation
inferred← citeshttps://doi.org/10.1145/3834569openalex-snapshot
FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage
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