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Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-46448-0_2openalex-snapshot
SSD: Single Shot MultiBox Detector
inferredcites →https://doi.org/10.1007/s11263-014-0733-5openalex-snapshot
The Pascal Visual Object Classes Challenge: A Retrospective
inferredcites →https://doi.org/10.1007/s11263-015-0816-yopenalex-snapshot
ImageNet Large Scale Visual Recognition Challenge
inferredcites →https://doi.org/10.1109/cvpr.2014.81openalex-snapshot
Rich Feature Hierarchies for Accurate Object Detection and Semantic Segmentation
inferredcites →https://doi.org/10.1109/cvpr.2016.91openalex-snapshot
You Only Look Once: Unified, Real-Time Object Detection
inferredcites →https://doi.org/10.1109/cvprw.2011.5981829openalex-snapshot
NeuFlow: A runtime reconfigurable dataflow processor for vision
inferredcites →https://doi.org/10.1109/fccm.2017.64openalex-snapshot
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1109/fpl.2016.7577308openalex-snapshot
A high performance FPGA-based accelerator for large-scale convolutional neural networks
inferredcites →https://doi.org/10.1109/fpl.2016.7577356openalex-snapshot
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA
inferredcites →https://doi.org/10.1109/fpt.2017.8280147openalex-snapshot
Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA
inferredcites →https://doi.org/10.1109/isca.2016.42openalex-snapshot
Cambricon: An Instruction Set Architecture for Neural Networks
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/jssc.2017.2749425openalex-snapshot
A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI
inferredcites →https://doi.org/10.1109/micro.2002.1176233openalex-snapshot
Proceedings 35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-35)
inferredcites →https://doi.org/10.1109/micro.2014.58openalex-snapshot
DaDianNao: A Machine-Learning Supercomputer
inferredcites →https://doi.org/10.1109/mm.2017.39openalex-snapshot
Software-Hardware Codesign for Efficient Neural Network Acceleration
inferredcites →https://doi.org/10.1109/tpami.2016.2577031openalex-snapshot
Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks
inferredcites →https://doi.org/10.1137/1.9781611970364openalex-snapshot
Arithmetic Complexity of Computations
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3020078.3021698openalex-snapshot
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3020078.3021727openalex-snapshot
Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System
inferredcites →https://doi.org/10.1145/3020078.3021738openalex-snapshot
An OpenCL™ Deep Learning Accelerator on Arria 10
inferredcites →https://doi.org/10.1145/3061639.3062244openalex-snapshot
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1145/3079758openalex-snapshot
Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot
Very Deep Convolutional Networks for Large-Scale Image Recognition
inferredcites →https://doi.org/10.48550/arxiv.1606.06160openalex-snapshot
DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
inferredcites →https://doi.org/10.48550/arxiv.1701.03534openalex-snapshot
An OpenCL(TM) Deep Learning Accelerator on Arria 10
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-74556-1_5openalex-snapshot
Minimal Filtering Algorithms for Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1007/s11554-020-00977-wopenalex-snapshot
A dedicated hardware accelerator for real-time acceleration of YOLOv2
inferred← citeshttps://doi.org/10.1109/access.2024.3510677openalex-snapshot
Comparative Survey of Embedded System Implementations of Convolutional Neural Networks in Autonomous Cars Applications
inferred← citeshttps://doi.org/10.1109/aicas48895.2020.9073925openalex-snapshot
Soft Error Mitigation for Deep Convolution Neural Network on FPGA Accelerators
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218717openalex-snapshot
INCA: INterruptible CNN Accelerator for Multi-tasking in Embedded Robots
inferred← citeshttps://doi.org/10.1109/edssc.2019.8754067openalex-snapshot
A FPGA-based Accelerator of Convolutional Neural Network for Face Feature Extraction
inferred← citeshttps://doi.org/10.1109/fccm48280.2020.00014openalex-snapshot
CNN-based Feature-point Extraction for Real-time Visual SLAM on Embedded FPGA
inferred← citeshttps://doi.org/10.1109/indiscon66021.2025.11254970openalex-snapshot
Designing of Intelligent Hardware System for Brain Tumor Detection
inferred← citeshttps://doi.org/10.1109/ipdpsw50202.2020.00019openalex-snapshot
CNN-based Monocular Decentralized SLAM on embedded FPGA
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00011openalex-snapshot
On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA
inferred← citeshttps://doi.org/10.1109/mcas.2021.3071609openalex-snapshot
A Survey of FPGA-Based Robotic Computing
inferred← citeshttps://doi.org/10.1109/tc.2021.3110413openalex-snapshot
OctCNN: A High Throughput FPGA Accelerator for CNNs using Octave Convolution Algorithm
inferred← citeshttps://doi.org/10.1109/tcad.2021.3072340openalex-snapshot
INCAME: Interruptible CNN Accelerator for Multirobot Exploration
inferred← citeshttps://doi.org/10.1109/tnnls.2020.2979682openalex-snapshot
Fast Algorithms for Quaternion-Valued Convolutional Neural Networks
inferred← citeshttps://doi.org/10.11591/ijece.v14i4.pp3863-3875openalex-snapshot
Field-programmable gate array implementation of efficient deep neural network architecture
inferred← citeshttps://doi.org/10.1360/ssi-2024-0351openalex-snapshot
FPGA Overlay processor for AI computing
inferred← citeshttps://doi.org/10.20944/preprints201903.0131.v1openalex-snapshot
Energy Consumption Prediction Using Machine Learning; A Review
inferred← citeshttps://doi.org/10.3390/electronics14061182openalex-snapshot
An Efficient Convolutional Neural Network Accelerator Design on FPGA Using the Layer-to-Layer Unified Input Winograd Architecture
inferred← citeshttps://doi.org/10.3390/rs16050894openalex-snapshot
An Overlay Accelerator of DeepLab CNN for Spacecraft Image Segmentation on FPGA
inferred← citeshttps://doi.org/10.3390/s21196491openalex-snapshot
A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System
inferred← citeshttps://doi.org/10.3390/s22165967openalex-snapshot
Design of Convolutional Neural Network Processor Based on FPGA Resource Multiplexing Architecture
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