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An Efficient Convolutional Neural Network Accelerator Design on FPGA Using the Layer-to-Layer Unified Input Winograd Architecture

https://doi.org/10.3390/electronics14061182

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Deep Residual Learning for Image Recognition

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Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs

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Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA

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Cryptensor: A Resource-Shared Co-Processor to Accelerate Convolutional Neural Network and Polynomial Convolution

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Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units

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Towards Reconfigurable CNN Accelerator for FPGA Implementation

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ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization

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Arithmetic Complexity of Computations

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ImageNet classification with deep convolutional neural networks

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Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA

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[DL] A Survey of FPGA-based Neural Network Inference Accelerators

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Accelerate Non-unit Stride Convolutions with Winograd Algorithms

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FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA

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Review of deep learning: concepts, CNN architectures, challenges, applications, future directions

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DWM: A Decomposable Winograd Method for Convolution Acceleration

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