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mNet2FPGA: A Design Flow for Mapping a Fixed-Point CNN to Zynq SoC FPGA
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-46493-0_32openalex-snapshot
XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
inferredcites →https://doi.org/10.1016/j.neucom.2017.09.046openalex-snapshot
FP-BNN: Binarized neural network on FPGA
inferredcites →https://doi.org/10.1109/fccm.2017.25openalex-snapshot
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
inferredcites →https://doi.org/10.1109/micro.2016.7783720openalex-snapshot
From high-level deep neural models to FPGAs
inferredcites →https://doi.org/10.1109/mm.2017.39openalex-snapshot
Software-Hardware Codesign for Efficient Neural Network Acceleration
inferredcites →https://doi.org/10.1109/tbcas.2018.2880012openalex-snapshot
Neuromorphic LIF Row-by-Row Multi-convolution Processor for FPGA
inferredcites →https://doi.org/10.1109/tcad.2017.2705069openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
inferredcites →https://doi.org/10.1109/tcad.2017.2785257openalex-snapshot
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tcad.2018.2857078openalex-snapshot
MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip
inferredcites →https://doi.org/10.1109/tcad.2018.2877016openalex-snapshot
Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems
inferredcites →https://doi.org/10.1109/tcad.2018.2884972openalex-snapshot
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators
inferredcites →https://doi.org/10.1109/tcsi.2017.2767204openalex-snapshot
Efficient Hardware Architectures for Deep Convolutional Neural Network
inferredcites →https://doi.org/10.1109/tnnls.2018.2852335openalex-snapshot
NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps
inferredcites →https://doi.org/10.1109/tnnls.2019.2911603openalex-snapshot
Convolutional Neural Networks as Asymmetric Volterra Models Based on Generalized Orthonormal Basis Functions
inferredcites →https://doi.org/10.1109/tnnls.2020.2980041openalex-snapshot
A Learning Framework for n-Bit Quantized Neural Networks Toward FPGAs
inferredcites →https://doi.org/10.1109/tvlsi.2019.2905242openalex-snapshot
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
inferredcites →https://doi.org/10.1109/tvlsi.2019.2913958openalex-snapshot
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
inferredcites →https://doi.org/10.1109/tvlsi.2019.2939726openalex-snapshot
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3186332openalex-snapshot
Toolflows for Mapping Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.14569/ijacsa.2018.091062openalex-snapshot
Fixed Point Implementation of Tiny-Yolo-v2 using OpenCL on FPGA
inferredcites →https://doi.org/10.23919/fpl.2017.8056828openalex-snapshot
Latency-driven design for FPGA-based convolutional neural networks
inferredcites →https://doi.org/10.48550/arxiv.1602.02830openalex-snapshot
Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1
inferredcites →https://doi.org/10.57702/o9raffedopenalex-snapshot
Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Deep CNN Co-design for HEVC CU Partition Prediction on FPGA–SoC
inferred← citeshttps://doi.org/10.1016/j.array.2026.100885openalex-snapshot
A numerical workflow for post-training fixed-point CNN deployment on FPGA
inferred← citeshttps://doi.org/10.1109/access.2022.3142292openalex-snapshot
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems
inferred← citeshttps://doi.org/10.1109/aiim60438.2023.10441025openalex-snapshot
Design of Handwritten Mongolian Recognition System Based on FPGA
inferred← citeshttps://doi.org/10.1109/icdv66179.2025.11135186openalex-snapshot
Efficient AI Model and Hardware Architecture Based on CNN for Arrhythmia Prediction
inferred← citeshttps://doi.org/10.1109/socc56010.2022.9908101openalex-snapshot
CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL
inferred← citeshttps://doi.org/10.18517/ijaseit.13.3.18456openalex-snapshot
Variable Precision Multiplier for CNN Accelerators Based on Booth Algorithm
inferred← citeshttps://doi.org/10.20334/2021-004-popenalex-snapshot
Vilniaus Gedimino technikos universitetas 2020 m.
inferred← citeshttps://doi.org/10.3390/agriculture12111849openalex-snapshot
FPGA Implementation of a Convolutional Neural Network and Its Application for Pollen Detection upon Entrance to the Beehive
inferred← citeshttps://doi.org/10.3390/app12115608openalex-snapshot
A System for a Real-Time Electronic Component Detection and Classification on a Conveyor Belt
inferred← citeshttps://doi.org/10.3390/electronics10020201openalex-snapshot
A Non-Linear Convolution Network for Image Processing
inferred← citeshttps://doi.org/10.3390/info16100914openalex-snapshot
Convolutional Neural Network Acceleration Techniques Based on FPGA Platforms: Principles, Methods, and Challenges
inferred← citeshttps://doi.org/10.3390/mi14122215openalex-snapshot
Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset
inferred← citeshttps://doi.org/10.3390/rs14133130openalex-snapshot
Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application
inferred← citeshttps://doi.org/10.3390/s22176618openalex-snapshot
A Hardware-Friendly Low-Bit Power-of-Two Quantization Method for CNNs and Its FPGA Implementation
inferred← citeshttps://doi.org/10.3390/s23146497openalex-snapshot
A Lightweight Detection Method for Remote Sensing Images and Its Energy-Efficient Accelerator on Edge Devices
inferred← citeshttps://doi.org/10.3390/s26051626openalex-snapshot
FPGA-Based CNN Acceleration on Zynq-7020 for Embedded Ship Recognition in Unmanned Surface Vehicles
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