On the public citation graph
Decoupled Fused Cache
0 signed · 53 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/4.509850openalex-snapshot
CACTI: an enhanced cache access and cycle time model
inferredcites →https://doi.org/10.1109/hpca.2010.5416636openalex-snapshot
Interval simulation: Raising the level of abstraction in architectural simulation
inferredcites →https://doi.org/10.1109/hpca.2016.7446068openalex-snapshot
Efficient footprint caching for Tagless DRAM Caches
inferredcites →https://doi.org/10.1109/hpca36999.2016openalex-snapshot
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)
inferredcites →https://doi.org/10.1109/isca.2008.15openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1109/l-ca.2012.2openalex-snapshot
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/micro.2012.30openalex-snapshot
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
inferredcites →https://doi.org/10.1109/micro.2012.31openalex-snapshot
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
inferredcites →https://doi.org/10.1109/micro.2014.36openalex-snapshot
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth
inferredcites →https://doi.org/10.1109/micro.2014.51openalex-snapshot
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
inferredcites →https://doi.org/10.1109/micro11684.2006openalex-snapshot
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)
inferredcites →https://doi.org/10.1109/mm.2012.25openalex-snapshot
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
inferredcites →https://doi.org/10.1109/tpds.2015.2461155openalex-snapshot
A Survey Of Techniques for Architecting DRAM Caches
inferredcites →https://doi.org/10.1109/tpds.2016.2546249openalex-snapshot
A Survey of Techniques for Architecting and Managing GPU Register File
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1250662.1250713openalex-snapshot
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
inferredcites →https://doi.org/10.1145/1273440.1250713openalex-snapshot
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
inferredcites →https://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1145/191995.192072openalex-snapshot
Decoupled sectored caches: conciliating low tag implementation cost
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2485922.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/2593069.2593197openalex-snapshot
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture
inferredcites →https://doi.org/10.1145/2749469.2750383openalex-snapshot
A fully associative, tagless DRAM cache
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/635506.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1177/109434209100500306openalex-snapshot
The NAS Parallel Benchmarks
inferredcites →https://doi.org/10.23919/date.2018.8342077openalex-snapshot
FusionCache: Using LLC tags for DRAM cache
inferredcites →https://doi.org/10.5555/211554.211583openalex-snapshot
Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
inferredcites →https://doi.org/10.5555/3195638.3195681openalex-snapshot
C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11390-023-2561-yopenalex-snapshot
P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00059openalex-snapshot
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071115openalex-snapshot
Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00017openalex-snapshot
Hydrogen: Contention-Aware Hybrid Memory for Heterogeneous CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/tc.2020.3029615openalex-snapshot
Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling
inferred← citeshttps://doi.org/10.1109/tc.2023.3251852openalex-snapshot
Object Fingerprint Cache for Heterogeneous Memory System
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012789openalex-snapshot
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities
inferred← citeshttps://doi.org/10.1109/tcad.2022.3231836openalex-snapshot
RHPM: Using Relative Hotness to Guide Page Migration for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tcad.2023.3333284openalex-snapshot
AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2019.2918385openalex-snapshot
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement
inferred← citeshttps://doi.org/10.1145/3449043openalex-snapshot
Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache
inferred← citeshttps://doi.org/10.1145/3451342openalex-snapshot
Performance Evaluation of Intel Optane Memory for Managed Workloads
inferred← citeshttps://doi.org/10.1145/3656019.3689612openalex-snapshot
Trimma: Trimming Metadata Storage and Latency for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3721145.3725776openalex-snapshot
MEMPLEX: A Memory System with Replication and Migration of Data for Multi-Chiplet NUMA Architectures
inferred← citeshttps://doi.org/10.3390/electronics9122061openalex-snapshot
Polymorphic Memory: A Hybrid Approach for Utilizing On-Chip Memory in Manycore Systems
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.