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A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2010.5416642openalex-snapshot
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
inferredcites →https://doi.org/10.1109/iccd.2007.4601880openalex-snapshot
Exploring DRAM cache architectures for CMP server platforms
inferredcites →https://doi.org/10.1109/isca.1990.134546openalex-snapshot
The TLB slice-a low-cost high-speed address translation mechanism
inferredcites →https://doi.org/10.1109/isca.1999.765938openalex-snapshot
Speculation techniques for improving load related instruction scheduling
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A 22nm IA multi-CPU and GPU System-on-Chip
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferredcites →https://doi.org/10.1109/mm.2008.44openalex-snapshot
System-Level Performance Metrics for Multiprogram Workloads
inferredcites →https://doi.org/10.1109/mm.2010.31openalex-snapshot
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2333660.2333752openalex-snapshot
Energy-efficient GPU design with reconfigurable in-package graphics memory
inferredcites →https://doi.org/10.1145/285930.285980openalex-snapshot
A study of branch prediction strategies
inferredcites →https://doi.org/10.1145/300979.300983openalex-snapshot
Speculation techniques for improving load related instruction scheduling
inferredcites →https://doi.org/10.1145/325096.325161openalex-snapshot
The TLB slice—a low-cost high-speed address translation mechanism
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme
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inferred← citeshttps://doi.org/10.1109/isca59077.2024.00086openalex-snapshot
Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers
inferred← citeshttps://doi.org/10.1109/micro.2014.36openalex-snapshot
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth
inferred← citeshttps://doi.org/10.1109/micro.2014.56openalex-snapshot
Transparent Hardware Management of Stacked DRAM as Part of Memory
inferred← citeshttps://doi.org/10.1109/micro.2014.63openalex-snapshot
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
inferred← citeshttps://doi.org/10.1109/micro.2016.7783738openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/sc.2016.75openalex-snapshot
DCA: A DRAM-cache-Aware DRAM Controller
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Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction
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eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache
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Trade-off between Hit Rate and Hit Latency for Optimizing DRAM Cache
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fPIM: A Holistic Design to Optimize PIM Data Flow for High Execution Efficiency
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CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache
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Performance and Energy-Efficient Design of STT-RAM Last-Level Cache
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Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs
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CAMO: a novel cache management organization for GPGPUs
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