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Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
inferredcites →https://doi.org/10.1109/hpca.2010.5416642openalex-snapshot
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
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Exploring DRAM cache architectures for CMP server platforms
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Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
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A modified approach to data cache management
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Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
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A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
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Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
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Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
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Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1854273.1854333openalex-snapshot
Using dead blocks as a virtual victim cache
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/781027.781076openalex-snapshot
Using SimPoint for accurate and efficient simulation
inferredcites →https://doi.org/10.5555/225160.225177openalex-snapshot
A modified approach to data cache management
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Flexible associativity for DRAM caches
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Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs
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MaPHeA: a lightweight memory hierarchy-aware profile-guided heap allocation framework
inferred← citeshttps://doi.org/10.1145/3466752.3480105openalex-snapshot
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources
inferred← citeshttps://doi.org/10.1145/3489517.3530570openalex-snapshot
Architecting DDR5 DRAM caches for non-volatile memory systems
inferred← citeshttps://doi.org/10.1145/3491045openalex-snapshot
Offline and Online Algorithms for SSD Management
inferred← citeshttps://doi.org/10.1145/3527853openalex-snapshot
MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap Allocation
inferred← citeshttps://doi.org/10.1145/3559009.3569649openalex-snapshot
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems
inferred← citeshttps://doi.org/10.1145/3565885openalex-snapshot
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations
inferred← citeshttps://doi.org/10.1145/3579436openalex-snapshot
SLITS: Sparsity-Lightened Intelligent Thread Scheduling
inferred← citeshttps://doi.org/10.1145/3631882.3631905openalex-snapshot
MC-ELMM: Multi-Chip Endurance-Limited Memory Management
inferred← citeshttps://doi.org/10.1145/3650200.3656612openalex-snapshot
HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory
inferred← citeshttps://doi.org/10.1145/3656019.3689612openalex-snapshot
Trimma: Trimming Metadata Storage and Latency for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3676966openalex-snapshot
Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems
inferred← citeshttps://doi.org/10.1145/3721145.3725776openalex-snapshot
MEMPLEX: A Memory System with Replication and Migration of Data for Multi-Chiplet NUMA Architectures
inferred← citeshttps://doi.org/10.1145/3736227.3736230openalex-snapshot
Exploiting Locality in Flat Memory with CXL for In-Memory Database Management Systems
inferred← citeshttps://doi.org/10.12794/metadc1505134openalex-snapshot
A Study on Flat-Address-Space Heterogeneous Memory Architectures
inferred← citeshttps://doi.org/10.1371/journal.pone.0257047openalex-snapshot
Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures
inferred← citeshttps://doi.org/10.15781/t2n58cp64openalex-snapshot
On-Chip Mechanisms to Reduce Effective Memory Access Latency
inferred← citeshttps://doi.org/10.1587/transele.2021lhp0004openalex-snapshot
A Metadata Prefetching Mechanism for Hybrid Memory Architectures
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