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Duality cache for data parallel acceleration

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/3dic.2013.6702348openalex-snapshot

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

inferredcites →https://doi.org/10.1109/40.592312openalex-snapshot

A case for intelligent RAM

inferredcites →https://doi.org/10.1109/hpca.2013.6522344openalex-snapshot

Scaling towards kilo-core processors with asymmetric high-radix topologies

inferredcites →https://doi.org/10.1109/hpca.2015.7056040openalex-snapshot

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

inferredcites →https://doi.org/10.1109/hpca.2017.21openalex-snapshot

Compute Caches

inferredcites →https://doi.org/10.1109/hpca.2017.55openalex-snapshot

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

inferredcites →https://doi.org/10.1109/iccad.2013.6691165openalex-snapshot

An efficient compiler framework for cache bypassing on GPUs

inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot

Rodinia: A benchmark suite for heterogeneous computing

inferredcites →https://doi.org/10.1109/iiswc.2014.6983053openalex-snapshot

Graph processing on GPUs: Where are the bottlenecks?

inferredcites →https://doi.org/10.1109/iiswc41457.2017openalex-snapshot

2017 IEEE International Symposium on Workload Characterization (IISWC)

inferredcites →https://doi.org/10.1109/isca.2016.12openalex-snapshot

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars

inferredcites →https://doi.org/10.1109/isca.2016.13openalex-snapshot

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

inferredcites →https://doi.org/10.1109/isca.2016.41openalex-snapshot

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory

inferredcites →https://doi.org/10.1109/isca.2018.00039openalex-snapshot

Enabling Scientific Computing on Memristive Accelerators

inferredcites →https://doi.org/10.1109/isca.2018.00040openalex-snapshot

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

inferredcites →https://doi.org/10.1109/ispass.2014.6844483openalex-snapshot

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

inferredcites →https://doi.org/10.1109/jssc.2013.2258815openalex-snapshot

An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family

inferredcites →https://doi.org/10.1109/jssc.2016.2515510openalex-snapshot

A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory

inferredcites →https://doi.org/10.1109/lca.2015.2414456openalex-snapshot

Ramulator: A Fast and Extensible DRAM Simulator

inferredcites →https://doi.org/10.1109/tec.1959.5222693openalex-snapshot

The CORDIC Trigonometric Computing Technique

inferredcites →https://doi.org/10.1145/1054943.1054946openalex-snapshot

A low cost, multithreaded processing-in-memory system

inferredcites →https://doi.org/10.1145/1478786.1478840openalex-snapshot

A unified algorithm for elementary functions

inferredcites →https://doi.org/10.1145/1815961.1816021openalex-snapshot

Debunking the 100X GPU vs. CPU myth

inferredcites →https://doi.org/10.1145/1816038.1816021openalex-snapshot

Debunking the 100X GPU vs. CPU myth

inferredcites →https://doi.org/10.1145/1854273.1854318openalex-snapshot

Ocelot

inferredcites →https://doi.org/10.1145/2304576.2304582openalex-snapshot

Characterizing and improving the use of demand-fetched caches in GPUs

inferredcites →https://doi.org/10.1145/2540708.2540725openalex-snapshot

RowClone

inferredcites →https://doi.org/10.1145/2600212.2600213openalex-snapshot

TOP-PIM

inferredcites →https://doi.org/10.1145/2749469.2750385openalex-snapshot

PIM-enabled instructions

inferredcites →https://doi.org/10.1145/275107.275139openalex-snapshot

A survey of CORDIC algorithms for FPGA based computers

inferredcites →https://doi.org/10.1145/279358.279387openalex-snapshot

Active pages: a computation model for intelligent memory

inferredcites →https://doi.org/10.1145/279361.279387openalex-snapshot

Active pages

inferredcites →https://doi.org/10.1145/3007787.3001139openalex-snapshot

ISAAC

inferredcites →https://doi.org/10.1145/3007787.3001140openalex-snapshot

PRIME

inferredcites →https://doi.org/10.1145/3173162.3173171openalex-snapshot

In-Memory Data Parallel Processor

inferredcites →https://doi.org/10.1145/781498.781505openalex-snapshot

Programming the FlexRAM parallel intelligent memory system

inferredcites →https://doi.org/10.1145/966049.781505openalex-snapshot

Programming the FlexRAM parallel intelligent memory system

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Hardware for Deep Learning Acceleration

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Introduction

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An Overview of Computation-in-Memory (CIM) Architectures

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A Case for Genome Analysis Where Genomes Reside

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A Modern Primer on Processing in Memory

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An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons

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CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing

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Invited: Accelerating Fully Homomorphic Encryption with Processing in Memory

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ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions

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In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips

inferred← citeshttps://doi.org/10.1109/dsn58291.2024.00024openalex-snapshot

Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis

inferred← citeshttps://doi.org/10.1109/dsn64029.2025.00018openalex-snapshot

Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory

inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00018openalex-snapshot

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00054openalex-snapshot

CAPE: A Content-Addressable Processing Engine

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00060openalex-snapshot

Stream Floating: Enabling Proactive and Decentralized Cache Optimizations

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00032openalex-snapshot

Near-Stream Computing: General and Transparent Near-Cache Acceleration

inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071074openalex-snapshot

EVE: Ephemeral Vector Engines

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00024openalex-snapshot

MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00045openalex-snapshot

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408599openalex-snapshot

The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution

inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323777openalex-snapshot

ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions

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High Throughput CNN Inference and Training with In-Cache Computation

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CIDAN: Computing in DRAM with Artificial Neurons

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DISCA:A Digital in-Memory Stochastic Computing Architecture Using a Compressed Bent-Pyramid Format

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Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-In-Memory Hardware

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REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute

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PipeIMC: A Pipelined In-SRAM Computing Architecture

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Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

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An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs

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Evaluating Machine LearningWorkloads on Memory-Centric Computing Systems

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TransPimLib: Efficient Transcendental Functions for Processing-in-Memory Systems

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Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation

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Exploiting Near-Data Processing to Accelerate Time Series Analysis

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Machine Learning Training on a Real Processing-in-Memory System

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Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture

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Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives

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Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

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An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS

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Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration

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Newton: A DRAM-maker’s Accelerator-in-Memory (AiM) Architecture for Machine Learning

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pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

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Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory

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3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit

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FloatAP: Supporting High-Performance Floating-Point Arithmetic in Associative Processors

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Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator

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gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM

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CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays

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Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks

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A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks

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RACER: Bit-Pipelined Processing Using Resistive Memory

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SortCache

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Processing-in-SRAM acceleration for ultra-low power visual 3D perception

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Inhale

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Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption

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A Survey on Memory-centric Computer Architectures

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PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

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MemFHE: End-to-end Computing with Fully Homomorphic Encryption in Memory

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Fusing In-storage and Near-storage Acceleration of Convolutional Neural Networks

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MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing

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Affinity Alloc: Taming Not-So Near-Data Computing

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PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation

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NUPEA: Optimizing Critical Loads on Spatial Dataflow Architectures via Non-Uniform Processing-Element Access

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DARTH-PUM: A Hybrid Processing-Using-Memory Architecture

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Accelerating irregular applications via efficient synchronization and data access techniques

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In-/Near-Memory Computing

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Hardware and algorithm co-optimization for energy-efficient machine learning integrated circuits

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Digital in-memory stochastic computing architecture for vector-matrix multiplication

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Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM

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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

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Accelerating Time Series Analysis via Processing using Non-Volatile Memories

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Proximu$: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute

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Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture

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SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM

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