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Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1088/1742-6596/78/1/012022openalex-snapshot
Understanding failures in petascale computers
inferredcites →https://doi.org/10.1109/cgo.2013.6495002openalex-snapshot
Idempotent code generation: Implementation, analysis, and evaluation
inferredcites →https://doi.org/10.1109/hpca.2017.50openalex-snapshot
ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging
inferredcites →https://doi.org/10.1109/hpca39059.2017openalex-snapshot
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
inferredcites →https://doi.org/10.1109/hpcs.2017.37openalex-snapshot
Accelerating Matrix Multiplication in Deep Learning by Using Low-Rank Approximation
inferredcites →https://doi.org/10.1109/iccd.2014.6974684openalex-snapshot
Loose-Ordering Consistency for persistent memory
inferredcites →https://doi.org/10.1109/ipdps.2013.69openalex-snapshot
Optimizing Checkpoints Using NVM as Virtual Memory
inferredcites →https://doi.org/10.1109/isca.2018.00044openalex-snapshot
Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/ispass.2015.7095793openalex-snapshot
Non-volatile memory host controller interface performance analysis in high-performance I/O systems
inferredcites →https://doi.org/10.1109/isscc.2007.373503openalex-snapshot
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read
inferredcites →https://doi.org/10.1109/jproc.2010.2070830openalex-snapshot
Resistive Random Access Memory (ReRAM) Based on Metal Oxides
inferredcites →https://doi.org/10.1109/micro.2018.00029openalex-snapshot
iDO: Compiler-Directed Failure Atomicity for Nonvolatile Memory
inferredcites →https://doi.org/10.1109/micro43151.2018openalex-snapshot
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
inferredcites →https://doi.org/10.1109/mm.2010.24openalex-snapshot
Phase-Change Technology and the Future of Main Memory
inferredcites →https://doi.org/10.1109/pact.2017.58openalex-snapshot
Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory
inferredcites →https://doi.org/10.1109/pact10394.2005openalex-snapshot
14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)
inferredcites →https://doi.org/10.1109/sc.2010.18openalex-snapshot
Design, Modeling, and Evaluation of a Scalable Multi-level Checkpointing System
inferredcites →https://doi.org/10.1109/vlsic.2004.1346644openalex-snapshot
An 8Mb demonstrator for high-density 1.8V Phase-Change Memories
inferredcites →https://doi.org/10.1145/1024393.1024421openalex-snapshot
Application-level checkpointing for shared memory programs
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/143365.143523openalex-snapshot
Fast mutual exclusion for uniprocessors
inferredcites →https://doi.org/10.1145/143365.143529openalex-snapshot
Sentinel scheduling for VLIW and superscalar processors
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1654059.1654117openalex-snapshot
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems
inferredcites →https://doi.org/10.1145/195473.195547openalex-snapshot
The performance advantages of integrating block data transfer in cache-coherent multiprocessors
inferredcites →https://doi.org/10.1145/2155620.2155637openalex-snapshot
Idempotent processor architecture
inferredcites →https://doi.org/10.1145/2254064.2254120openalex-snapshot
Static analysis and compiler design for idempotent processing
inferredcites →https://doi.org/10.1145/2830772.2830805openalex-snapshot
Efficient persist barriers for multicores
inferredcites →https://doi.org/10.1145/2872362.2872381openalex-snapshot
High-Performance Transactions for Persistent Memories
inferredcites →https://doi.org/10.1145/2872362.2872410openalex-snapshot
Failure-Atomic Persistent Memory Updates via JUSTDO Logging
inferredcites →https://doi.org/10.1145/2925426.2926284openalex-snapshot
Write-Aware Management of NVM-based Memory Extensions
inferredcites →https://doi.org/10.1145/3079856.3080240openalex-snapshot
Hiding the Long Latency of Persist Barriers Using Speculative Execution
inferredcites →https://doi.org/10.1145/3192366.3192367openalex-snapshot
Persistency for synchronization-free regions
inferredcites →https://doi.org/10.1177/1094342015570921openalex-snapshot
A checkpoint compression study for high-performance computing systems
inferredcites →https://doi.org/10.5555/3014904.3014931openalex-snapshot
Compiler-directed lightweight checkpointing for fine-grained guaranteed soft error recovery
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10586-025-05130-5openalex-snapshot
An efficient low aggressiveness portion (ELAP) cache replacement policy for systems with non-volatile main memory
inferred← citeshttps://doi.org/10.1109/aero66936.2026.11520060openalex-snapshot
Mitigating Single-Event Functional Interrupts in the Peripheral Circuitry of Non-Volatile Memories in Radiation Environments
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218612openalex-snapshot
WET: Write Efficient Loop Tiling for Non-Volatile Main Memory
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00019openalex-snapshot
BBB: Simplifying Persistent Programming using Battery-Backed Buffers
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071088openalex-snapshot
Reconciling Selective Logging and Hardware Persistent Memory Transaction
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00015openalex-snapshot
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback
inferred← citeshttps://doi.org/10.1109/tc.2020.2988251openalex-snapshot
Idempotence-Based Preemptive GPU Kernel Scheduling for Embedded Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2022.3183793openalex-snapshot
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories
inferred← citeshttps://doi.org/10.1145/3371236openalex-snapshot
Compiler-support for Critical Data Persistence in NVM
inferred← citeshttps://doi.org/10.1145/3445814.3446730openalex-snapshot
Clobber-NVM: log less, re-execute more
inferred← citeshttps://doi.org/10.1145/3629524openalex-snapshot
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing
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