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On-the-fly Page Migration and Address Reconciliation for Heterogeneous Memory Systems

https://doi.org/10.1145/3364179
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-54999-6_10openalex-snapshot
HBM-Resident Prefetching for Heterogeneous Memory System
inferredcites →https://doi.org/10.1016/j.future.2017.06.012openalex-snapshot
Refinery swap: An efficient swap mechanism for hybrid DRAM–NVM systems
inferredcites →https://doi.org/10.1016/j.sysarc.2015.07.009openalex-snapshot
Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy
inferredcites →https://doi.org/10.1109/clustr.2009.5289173openalex-snapshot
Analytical modeling and optimization for affinity based thread scheduling on multicore systems
inferredcites →https://doi.org/10.1109/codit.2018.8394925openalex-snapshot
NUMA-BTLP: A static algorithm for thread classification
inferredcites →https://doi.org/10.1109/hpca.2010.5416642openalex-snapshot
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
inferredcites →https://doi.org/10.1109/hpca.2010.5416643openalex-snapshot
UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all
inferredcites →https://doi.org/10.1109/micro.2014.51openalex-snapshot
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
inferredcites →https://doi.org/10.1109/micro.2014.56openalex-snapshot
Transparent Hardware Management of Stacked DRAM as Part of Memory
inferredcites →https://doi.org/10.1109/pact.2002.1105967openalex-snapshot
Proceedings 2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002
inferredcites →https://doi.org/10.1109/pact.2017.38openalex-snapshot
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries
inferredcites →https://doi.org/10.1145/1555815.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2490301.2451157openalex-snapshot
Traffic management
inferredcites →https://doi.org/10.1145/2508148.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/2597917.2597924openalex-snapshot
Concurrent page migration for mobile systems with OS-managed hybrid memory
inferredcites →https://doi.org/10.1145/2628071.2628085openalex-snapshot
kMAF
inferredcites →https://doi.org/10.1145/3123939.3124555openalex-snapshot
Banshee
inferredcites →https://doi.org/10.2172/1117905openalex-snapshot
Hydrodynamics challenge problem
inferredcites →https://doi.org/10.2200/s00381ed1v01y201109cac018openalex-snapshot
Phase Change Memory: From Devices to Systems
inferredcites →https://doi.org/10.23919/date.2019.8715118openalex-snapshot
UIMigrate: Adaptive Data Migration for Hybrid Non-Volatile Memory Systems

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-70947-0_3openalex-snapshot
A Leap of Confidence: A Write-Intensity Aware Prudent Page Migration for Hybrid Memories
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103174openalex-snapshot
Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories
inferred← citeshttps://doi.org/10.1080/02564602.2022.2127945openalex-snapshot
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/iccd63220.2024.00077openalex-snapshot
Opportunistic Migration for Hybrid Memories While Mitigating Aging Effects
inferred← citeshttps://doi.org/10.1109/ispa63168.2024.00035openalex-snapshot
A Hybrid Memory Data Placement Strategy for Edge Computing
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528735openalex-snapshot
Write Intensity based Foresightful Page Migration for Hybrid memories
inferred← citeshttps://doi.org/10.1109/sbac-pad59825.2023.00017openalex-snapshot
A Practical Approach For Workload-Aware Data Movement in Disaggregated Memory Systems
inferred← citeshttps://doi.org/10.1109/tc.2026.3655315openalex-snapshot
S-Tiering: A Unified HW/SW Solution for Memory Tiering Based on the Standard CXL Hotness Monitoring Unit
inferred← citeshttps://doi.org/10.1109/tcad.2023.3333284openalex-snapshot
AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/vlsi-soc57769.2023.10321920openalex-snapshot
Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
inferred← citeshttps://doi.org/10.1145/3444750openalex-snapshot
Dynamically Adapting Page Migration Policies Based on Applications’ Memory Access Behaviors
inferred← citeshttps://doi.org/10.1145/3526241.3530327openalex-snapshot
SRS-Mig
inferred← citeshttps://doi.org/10.1145/3615979.3656059openalex-snapshot
DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems
inferred← citeshttps://doi.org/10.1145/3650200.3656612openalex-snapshot
HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory
inferred← citeshttps://doi.org/10.1145/3725218openalex-snapshot
CosMoS: Architectural Support for Cost-Effective Data Movement in a Disaggregated Memory Systems
inferred← citeshttps://doi.org/10.12794/metadc1873542openalex-snapshot
Improving Memory Performance for Both High Performance Computing and Embedded/Edge Computing Systems
inferred← citeshttps://doi.org/10.21203/rs.3.rs-2597744/v1openalex-snapshot
Design, Modeling, and Analysis of Memory Allocation Policies for Rack-Scale Memory Disaggregation
inferred← citeshttps://doi.org/10.48550/arxiv.2305.09977openalex-snapshot
DRackSim: Simulator for Rack-scale Memory Disaggregation
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