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ShiftsReduce
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.4380220202openalex-snapshot
Optimizing stack frame accesses for processors with restricted addressing modes
inferredcites →https://doi.org/10.1007/3-540-36579-6_21openalex-snapshot
Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms
inferredcites →https://doi.org/10.1007/3-540-45574-4_11openalex-snapshot
Improving Offset Assignment for Embedded Processors
inferredcites →https://doi.org/10.1007/s11390-016-1610-1openalex-snapshot
Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs
inferredcites →https://doi.org/10.1023/a:1024597010150openalex-snapshot
Hybrid Analysis: Static & Dynamic Memory Reference Analysis
inferredcites →https://doi.org/10.1038/nmat3020openalex-snapshot
Fast current-induced domain-wall motion controlled by the Rashba effect
inferredcites →https://doi.org/10.1038/nnano.2013.102openalex-snapshot
Chiral spin torque at magnetic domain walls
inferredcites →https://doi.org/10.1038/nnano.2014.324openalex-snapshot
Domain-wall velocities of up to 750 m s−1 driven by exchange-coupling torque in synthetic antiferromagnets
inferredcites →https://doi.org/10.1063/1.30199openalex-snapshot
The use of bubble lattices for information storage
inferredcites →https://doi.org/10.1103/physrevlett.98.037204openalex-snapshot
Current Driven Domain Wall Velocities Exceeding the Spin Angular Momentum Transfer Rate in Permalloy Nanowires
inferredcites →https://doi.org/10.1109/aspdac.2015.7058988openalex-snapshot
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power
inferredcites →https://doi.org/10.1109/aspdac.2015.7059042openalex-snapshot
Multilane Racetrack caches: Improving efficiency through compression and independent shifting
inferredcites →https://doi.org/10.1109/aspdac.2016.7427984openalex-snapshot
Performance-centric register file design for GPUs using racetrack memory
inferredcites →https://doi.org/10.1109/cases.2015.7324558openalex-snapshot
Reducing shift penalty in Domain Wall Memory through register locality
inferredcites →https://doi.org/10.1109/cluster.2017.50openalex-snapshot
Automating the Application Data Placement in Hybrid Memory Systems
inferredcites →https://doi.org/10.1109/clustr.2000openalex-snapshot
Proceedings IEEE International Conference on Cluster Computing. CLUSTER 2000
inferredcites →https://doi.org/10.1109/dac.2014.6881523openalex-snapshot
Exploration of GPGPU register file architecture using domain-wall-shift-write based racetrack memory
inferredcites →https://doi.org/10.1109/ftfc.2013.6577771openalex-snapshot
Racetrack memory based reconfigurable computing
inferredcites →https://doi.org/10.1109/iccad.1996.569409openalex-snapshot
Algorithms for address assignment in DSP code generation
inferredcites →https://doi.org/10.1109/iccd.2012.6378661openalex-snapshot
Row buffer locality aware caching policies for hybrid memories
inferredcites →https://doi.org/10.1109/islped.2019.8824954openalex-snapshot
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/isss.1998.730589openalex-snapshot
A uniform optimization technique for offset assignment problems
inferredcites →https://doi.org/10.1109/lca.2019.2899306openalex-snapshot
RTSim: A Cycle-Accurate Simulator for Racetrack Memories
inferredcites →https://doi.org/10.1109/mm.2010.24openalex-snapshot
Phase-Change Technology and the Future of Main Memory
inferredcites →https://doi.org/10.1109/nvmsa.2015.7304358openalex-snapshot
Exploring data placement in racetrack memory based scratchpad memory
inferredcites →https://doi.org/10.1109/pact.2015.10openalex-snapshot
Exploiting Program Semantics to Place Data in Hybrid Memory
inferredcites →https://doi.org/10.1109/tmag.2012.2198876openalex-snapshot
Ultra-High Density Content Addressable Memory Based on Current Induced Domain Wall Motion in Magnetic Track
inferredcites →https://doi.org/10.1109/tmag.2012.2203589openalex-snapshot
The Prospect of STT-RAM Scaling From Readability Perspective
inferredcites →https://doi.org/10.1109/tmscs.2016.2536020openalex-snapshot
FusedCache: A Naturally Inclusive, Racetrack Memory, Dual-Level Private Cache
inferredcites →https://doi.org/10.1109/tpds.2014.2324563openalex-snapshot
A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches
inferredcites →https://doi.org/10.1109/tpds.2015.2442980openalex-snapshot
A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems
inferredcites →https://doi.org/10.1109/tvlsi.2013.2278295openalex-snapshot
Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems
inferredcites →https://doi.org/10.1109/tvlsi.2016.2537400openalex-snapshot
Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory
inferredcites →https://doi.org/10.1109/tvlsi.2018.2804938openalex-snapshot
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache
inferredcites →https://doi.org/10.1126/science.1145799openalex-snapshot
Magnetic Domain-Wall Racetrack Memory
inferredcites →https://doi.org/10.1145/1555815.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555815.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/207110.207139openalex-snapshot
Storage assignment to decrease code size
inferredcites →https://doi.org/10.1145/223428.207139openalex-snapshot
Storage assignment to decrease code size
inferredcites →https://doi.org/10.1145/2463209.2488799openalex-snapshot
Cross-layer racetrack memory design for ultra high density and low power consumption
inferredcites →https://doi.org/10.1145/2463596.2463601openalex-snapshot
Solving the simple offset assignment problem as a traveling salesman
inferredcites →https://doi.org/10.1145/2609248.2609251openalex-snapshot
Optimal general offset assignment
inferredcites →https://doi.org/10.1145/2627369.2627651openalex-snapshot
Design exploration of racetrack lower-level caches
inferredcites →https://doi.org/10.1145/2669365openalex-snapshot
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories
inferredcites →https://doi.org/10.1145/3092255.3092273openalex-snapshot
RTHMS: a tool for data placement on hybrid memory system
inferredcites →https://doi.org/10.1145/3126543openalex-snapshot
A DWM-Based Stack Architecture Implementation for Energy Harvesting Systems
inferredcites →https://doi.org/10.1145/3156685.3092273openalex-snapshot
RTHMS: a tool for data placement on hybrid memory system
inferredcites →https://doi.org/10.1145/3287624openalex-snapshot
Proceedings of the 24th Asia and South Pacific Design Automation Conference
inferredcites →https://doi.org/10.1145/3316482.3326351openalex-snapshot
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads
inferredcites →https://doi.org/10.1145/800015openalex-snapshot
Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84
inferredcites →https://doi.org/10.1145/800053openalex-snapshot
Proceedings of the 7th annual symposium on Computer Architecture - ISCA '80
inferredcites →https://doi.org/10.1145/800094.803044openalex-snapshot
Intelligent magnetic bubble memories
inferredcites →https://doi.org/10.1147/rd.206.0576openalex-snapshot
Data Organization in Magnetic Bubble Lattice Files
inferredcites →https://doi.org/10.4230/lites-v002-i001-a002openalex-snapshot
More General Optimal Offset Assignment
inferredcites →https://doi.org/10.7873/date2014.172openalex-snapshot
Accelerating graph computation with racetrack memory and pointer-assisted graph representation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10825-020-01648-6openalex-snapshot
Spintronic devices: a promising alternative to CMOS devices
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.102837openalex-snapshot
An energy-efficient cache replacement policy for ultra-dense racetrack memory
inferred← citeshttps://doi.org/10.1063/5.0039509openalex-snapshot
Tip-induced flexoelectricity, polar vortices, and magnetic moments in ferroelastic materials
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586167openalex-snapshot
BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00075openalex-snapshot
Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory
inferred← citeshttps://doi.org/10.1109/icces54183.2022.9835778openalex-snapshot
A Review on Emerging Spintronic Devices: CMOS Counterparts
inferred← citeshttps://doi.org/10.1109/isit45174.2021.9518271openalex-snapshot
Coding for Transverse-Reads in Domain Wall Memories
inferred← citeshttps://doi.org/10.1109/ispa67752.2025.00043openalex-snapshot
RAR: Remapping Algorithm of Racetrack Memory Based Main-Memory for Parallelism Improvement
inferred← citeshttps://doi.org/10.1109/jproc.2020.2975719openalex-snapshot
Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade
inferred← citeshttps://doi.org/10.1109/jsait.2023.3334303openalex-snapshot
Transverse-Read-Codes for Domain Wall Memories
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00060openalex-snapshot
CORUSCANT: Fast Efficient Processing-in-Racetrack Memories
inferred← citeshttps://doi.org/10.1109/mm.2022.3195761openalex-snapshot
POD-RACING: Bulk-Bitwise to Floating-Point Compute in Racetrack Memory for Machine Learning at the Edge
inferred← citeshttps://doi.org/10.1109/nvmsa66678.2025.00018openalex-snapshot
Software-Hardware Co-Design for Feature Extraction on Racetrack Memory-Based PIM
inferred← citeshttps://doi.org/10.1109/socc49529.2020.9524792openalex-snapshot
Architectural Exploration on Racetrack Memories
inferred← citeshttps://doi.org/10.1109/tc.2020.3045433openalex-snapshot
An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNs
inferred← citeshttps://doi.org/10.1109/tc.2021.3117439openalex-snapshot
Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory
inferred← citeshttps://doi.org/10.1109/tc.2022.3148858openalex-snapshot
MemUnison: A Racetrack-ReRAM-combined Pipeline Architecture for Energy-Efficient in-Memory CNNs
inferred← citeshttps://doi.org/10.1109/tc.2022.3188206openalex-snapshot
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT
inferred← citeshttps://doi.org/10.1109/tc.2022.3197094openalex-snapshot
ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees
inferred← citeshttps://doi.org/10.1109/tc.2023.3257509openalex-snapshot
DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories
inferred← citeshttps://doi.org/10.1109/tc.2025.3575909openalex-snapshot
Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012266openalex-snapshot
Polyhedral Compilation for Racetrack Memories
inferred← citeshttps://doi.org/10.1109/tcad.2022.3161198openalex-snapshot
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture
inferred← citeshttps://doi.org/10.1109/tcad.2022.3185548openalex-snapshot
Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded Systems
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3161594openalex-snapshot
Pinning Fault Mode Modeling for DWM Shifting
inferred← citeshttps://doi.org/10.1109/tetc.2026.3696641openalex-snapshot
Inter-Set Correlation-Aware Replacement Policy for Energy Efficient RTM-Based Caches
inferred← citeshttps://doi.org/10.1109/tnano.2022.3158889openalex-snapshot
XDWM: A 2D Domain Wall Memory
inferred← citeshttps://doi.org/10.1145/3316482.3326351openalex-snapshot
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads
inferred← citeshttps://doi.org/10.1145/3396235openalex-snapshot
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories
inferred← citeshttps://doi.org/10.1145/3524071openalex-snapshot
Brain-inspired Cognition in Next-generation Racetrack Memories
inferred← citeshttps://doi.org/10.1145/3607889.3609088openalex-snapshot
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications
inferred← citeshttps://doi.org/10.1145/3645112openalex-snapshot
SPIMulator: A Spintronic Processing-in-memory Simulator for Racetracks
inferred← citeshttps://doi.org/10.1145/3748522.3779751openalex-snapshot
Sustaining Bε-Tree Efficiency on Single-Access-Port Racetrack Memory in Cyber-Physical System
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116245openalex-snapshot
Generalized Data Placement Strategies for Racetrack Memories
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