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Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11265-015-1088-zopenalex-snapshot
Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1016/j.micpro.2012.08.005openalex-snapshot
Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip
inferredcites →https://doi.org/10.1016/j.sysarc.2010.04.007openalex-snapshot
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
inferredcites →https://doi.org/10.1016/j.sysarc.2012.10.004openalex-snapshot
A survey on application mapping strategies for Network-on-Chip design
inferredcites →https://doi.org/10.1016/j.sysarc.2015.06.001openalex-snapshot
Dynamic task mapping for Network-on-Chip based systems
inferredcites →https://doi.org/10.1016/j.sysarc.2015.07.014openalex-snapshot
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes
inferredcites →https://doi.org/10.1016/j.sysarc.2017.01.008openalex-snapshot
Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform
inferredcites →https://doi.org/10.1049/iet-cdt.2010.0030openalex-snapshot
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration
inferredcites →https://doi.org/10.1109/dac.1992openalex-snapshot
[1992] Proceedings 29th ACM/IEEE Design Automation Conference
inferredcites →https://doi.org/10.1109/dac.1997openalex-snapshot
Proceedings of the 34th Design Automation Conference
inferredcites →https://doi.org/10.1109/date.2004openalex-snapshot
Proceedings Design, Automation and Test in Europe Conference and Exhibition
inferredcites →https://doi.org/10.1109/date.2010.5457211openalex-snapshot
An industrial design space exploration framework for supporting run-time resource management on multi-core systems
inferredcites →https://doi.org/10.1109/icmlc.2004.1382256openalex-snapshot
Proceedings of 2004 International Conference on Machine Learning and Cybernetics
inferredcites →https://doi.org/10.1109/isvlsi.2004.1339494openalex-snapshot
Proceedings IEEE Computer Society Annual Symposium on VLSI
inferredcites →https://doi.org/10.1109/les.2015.2402197openalex-snapshot
ORION3.0: A Comprehensive NoC Router Estimation Tool
inferredcites →https://doi.org/10.1109/tcad.2009.2034348openalex-snapshot
Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip
inferredcites →https://doi.org/10.1109/tcad.2015.2446938openalex-snapshot
Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs
inferredcites →https://doi.org/10.1109/tvlsi.2013.2240708openalex-snapshot
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization
inferredcites →https://doi.org/10.1145/1403375.1403675openalex-snapshot
User-aware dynamic task allocation in networks-on-chip
inferredcites →https://doi.org/10.1145/2390191.2390200openalex-snapshot
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
inferredcites →https://doi.org/10.1145/2442116.2442125openalex-snapshot
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
inferredcites →https://doi.org/10.1145/2556944openalex-snapshot
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration
inferredcites →https://doi.org/10.1145/2680542openalex-snapshot
A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1145/2953878openalex-snapshot
Cycle-Accurate Network on Chip Simulation with Noxim
inferredcites →https://doi.org/10.1145/3055512openalex-snapshot
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform
inferredcites →https://doi.org/10.1587/elex.5.464openalex-snapshot
DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip
inferredcites →https://doi.org/10.4230/lites-v004-i002-a001openalex-snapshot
Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-021-03764-xopenalex-snapshot
Reliability-aware task scheduling for energy efficiency on heterogeneous multiprocessor systems
inferred← citeshttps://doi.org/10.1016/j.jpdc.2024.104915openalex-snapshot
Energy-efficient triple modular redundancy scheduling on heterogeneous multi-core real-time systems
inferred← citeshttps://doi.org/10.1016/j.micpro.2023.104970openalex-snapshot
Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey
inferred← citeshttps://doi.org/10.1109/discover66922.2025.11258977openalex-snapshot
Adaptive and Fault-Tolerant Task Scheduling for 2D Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1109/norcas66540.2025.11231315openalex-snapshot
ATAS-HM: Adaptive Task Allocation for Real-Time Tasks on Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1109/tpds.2022.3177957openalex-snapshot
Run-Time Remapping Algorithm of Dataflow Actors on NoC-Based Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1109/tpds.2025.3601993openalex-snapshot
Mapping Large-Scale Spiking Neural Network on Arbitrary Meshed Neuromorphic Hardware
inferred← citeshttps://doi.org/10.1109/vdat63601.2024.10705675openalex-snapshot
An Adaptive Strategy for Dynamic Resource Allocation and Scheduling for Multitasking NoC based Multicore Systems
inferred← citeshttps://doi.org/10.1142/s0218126625504080openalex-snapshot
Performance Evaluation of a Novel EPO-FMPTMS Scheduling Technique for Balancing Traffic Patterns on NOC-Based Communication Infrastructure
inferred← citeshttps://doi.org/10.1145/3478288openalex-snapshot
Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Program Inputs
inferred← citeshttps://doi.org/10.1145/3575757.3593650openalex-snapshot
Task and Memory Mapping of Large Size Embedded Applications over NUMA architecture✱
inferred← citeshttps://doi.org/10.3390/electronics11010049openalex-snapshot
Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm
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