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Trust in FPGA-accelerated Cloud Computing
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-030-17227-5_11openalex-snapshot
Secure Local Configuration of Intellectual Property Without a Trusted Third Party
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_84openalex-snapshot
A Runtime Environment for Reconfigurable Hardware Operating Systems
inferredcites →https://doi.org/10.1007/978-3-642-00641-8_8openalex-snapshot
A Protocol for Secure Remote Updates of FPGA Configurations
inferredcites →https://doi.org/10.1007/978-3-642-04444-1_22openalex-snapshot
Enabling Public Verifiability and Data Dynamics for Storage Security in Cloud Computing
inferredcites →https://doi.org/10.1007/978-90-481-9157-4openalex-snapshot
Handbook of FPGA Design Security
inferredcites →https://doi.org/10.1007/s00145-010-9083-9openalex-snapshot
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA
inferredcites →https://doi.org/10.1007/s13389-016-0132-7openalex-snapshot
Interdiction in practice—Hardware Trojan against a high-security USB flash drive
inferredcites →https://doi.org/10.1109/access.2017.2661582openalex-snapshot
Virtualized Execution Runtime for FPGA Accelerators in the Cloud
inferredcites →https://doi.org/10.1109/fccm.2011.48openalex-snapshot
FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators
inferredcites →https://doi.org/10.1109/fccm.2018.00016openalex-snapshot
FPGA Side Channel Attacks without Physical Access
inferredcites →https://doi.org/10.1109/fpl.2010.44openalex-snapshot
Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA
inferredcites →https://doi.org/10.1109/fpl.2012.6339241openalex-snapshot
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration
inferredcites →https://doi.org/10.1109/fpl.2012.6339242openalex-snapshot
FPGAs for trusted cloud computing
inferredcites →https://doi.org/10.1109/fpl.2018.00031openalex-snapshot
A Survey on FPGA Virtualization
inferredcites →https://doi.org/10.1109/fpt.2007.4439246openalex-snapshot
Dynamic Intellectual Property Protection for Reconfigurable Devices
inferredcites →https://doi.org/10.1109/hoti.2017.13openalex-snapshot
An FPGA Platform for Hyperscalers
inferredcites →https://doi.org/10.1109/hpca.2019.00052openalex-snapshot
FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
inferredcites →https://doi.org/10.1109/ieeestd.2015.7274481openalex-snapshot
IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)
inferredcites →https://doi.org/10.1109/isvlsi.2008.61openalex-snapshot
SeReCon: A Secure Dynamic Partial Reconfiguration Controller
inferredcites →https://doi.org/10.1109/jproc.2014.2331672openalex-snapshot
FPGA Security: Motivations, Features, and Applications
inferredcites →https://doi.org/10.1109/mdat.2017.2741464openalex-snapshot
FASTEN: An FPGA-Based Secure System for Big Data Processing
inferredcites →https://doi.org/10.1109/reconfig.2013.6732330openalex-snapshot
A single-chip solution for the secure remote configuration of FPGAs using bitstream compression
inferredcites →https://doi.org/10.1109/sp.2018.00049openalex-snapshot
FPGA-Based Remote Power Side-Channel Attacks
inferredcites →https://doi.org/10.1109/tc.2017.2647955openalex-snapshot
Hardware-Based Trusted Computing Architectures for Isolation and Attestation
inferredcites →https://doi.org/10.1109/tifs.2011.2169667openalex-snapshot
A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs
inferredcites →https://doi.org/10.1109/tifs.2014.2355043openalex-snapshot
A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs
inferredcites →https://doi.org/10.1145/1331331.1331338openalex-snapshot
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
inferredcites →https://doi.org/10.1145/2046707.2046722openalex-snapshot
On the vulnerability of FPGA bitstream encryption against power analysis attacks
inferredcites →https://doi.org/10.1145/2487726.2488368openalex-snapshot
Innovative instructions and software model for isolated execution
inferredcites →https://doi.org/10.1145/3124680.3124743openalex-snapshot
The Feniks FPGA Operating System for Cloud Computing
inferredcites →https://doi.org/10.1145/3133956.3134040openalex-snapshot
Standardizing Bad Cryptographic Practice
inferredcites →https://doi.org/10.1145/3373087.3375322openalex-snapshot
Fingerprinting Cloud FPGA Infrastructures
inferredcites →https://doi.org/10.13154/tches.v2020.i3.169-195openalex-snapshot
JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms
inferredcites →https://doi.org/10.23919/date.2019.8714775openalex-snapshot
SACHa: Self-Attestation of Configurable Hardware
inferredcites →https://doi.org/10.46586/tches.v2018.i3.44-68openalex-snapshot
FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES
inferredcites →https://doi.org/10.46586/tches.v2018.i3.573-595openalex-snapshot
Key Extraction Using Thermal Laser Stimulation
inferredcites →https://doi.org/10.48550/arxiv.2005.04867openalex-snapshot
Security of Cloud FPGAs: A Survey
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-16344-9_14openalex-snapshot
FPGA Security: Security Threats from Untrusted FPGA CAD Toolchain
inferred← citeshttps://doi.org/10.1007/978-3-031-22170-5_3openalex-snapshot
AI Accelerators for Cloud and Server Applications
inferred← citeshttps://doi.org/10.1007/978-3-031-81213-2_7openalex-snapshot
Power Up IoT: How Hardware-Assisted Blockchain Is Transforming Connectivity in Health Care
inferred← citeshttps://doi.org/10.1007/s11227-025-07340-5openalex-snapshot
Toward secure program execution in multi-tenant cloud FPGA environments
inferred← citeshttps://doi.org/10.1007/s11704-022-2127-0openalex-snapshot
FPGA sharing in the cloud: a comprehensive analysis
inferred← citeshttps://doi.org/10.1007/s41635-023-00135-1openalex-snapshot
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
inferred← citeshttps://doi.org/10.1016/j.asoc.2026.115240openalex-snapshot
Dynamic trust evaluation based on heterogeneous graph convolution network and lightweight attention
inferred← citeshttps://doi.org/10.1016/j.cose.2023.103095openalex-snapshot
Design and implementation of trusted boot based on a new trusted computing dual-architecture
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103779openalex-snapshot
Beneath the fabric: A survey on threats and opportunities in reconfigurable systems
inferred← citeshttps://doi.org/10.1109/access.2023.3261802openalex-snapshot
A Survey of Trusted Computing Solutions Using FPGAs
inferred← citeshttps://doi.org/10.1109/access.2023.3331507openalex-snapshot
FPGA Bitstream Modification: Attacks and Countermeasures
inferred← citeshttps://doi.org/10.1109/access.2024.3353134openalex-snapshot
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/access.2025.3635270openalex-snapshot
Rethinking Trusted Execution Environments in the Age of Reconfigurable Computing
inferred← citeshttps://doi.org/10.1109/acsac63791.2024.00027openalex-snapshot
T-Edge: Trusted Heterogeneous Edge Computing
inferred← citeshttps://doi.org/10.1109/asianhost59942.2023.10409376openalex-snapshot
DF-TEE: Trusted Execution Environment for Disaggregated Multi-FPGA Cloud Systems
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00036openalex-snapshot
Trusted Configuration in Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133074openalex-snapshot
OMT: A Run-time Adaptive Architectural Framework for Bonsai Merkle Tree-Based Secure Authentication with Embedded Heterogeneous Memory
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545394openalex-snapshot
CTR+: A High-Performance Metadata Access Scheme for Secure Embedded Memory in Heterogeneous Computing Systems
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240860openalex-snapshot
FPGA-CC: Confidential Containers for Virtualized FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00007openalex-snapshot
A Tenant Side Compilation Solution for Cloud FPGA Deployment
inferred← citeshttps://doi.org/10.1109/iemcon56893.2022.9946490openalex-snapshot
Memory Isolation for Multi-Tenant Data Integrity in Cloud MPSoC FPGAs
inferred← citeshttps://doi.org/10.1109/iolts59296.2023.10224883openalex-snapshot
ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules
inferred← citeshttps://doi.org/10.1109/ipdpsw59300.2023.00025openalex-snapshot
Is Your FPGA Transmitting Secrets: Covert Antennas from Interconnect
inferred← citeshttps://doi.org/10.1109/isaics66888.2025.11350282openalex-snapshot
Research on the Security of SRAM base FPGAs in the Era of Artificial Intelligence
inferred← citeshttps://doi.org/10.1109/ispcc66872.2025.11039435openalex-snapshot
Enhancing FPGA Security: An AI-Driven Approach to Root of Trust Architecture
inferred← citeshttps://doi.org/10.1109/isqed57927.2023.10129405openalex-snapshot
Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00058openalex-snapshot
New Security Threats on FPGAs: From FPGA Design Tools Perspective
inferred← citeshttps://doi.org/10.1109/jproc.2023.3330729openalex-snapshot
A Visionary Look at the Security of Reconfigurable Cloud Computing
inferred← citeshttps://doi.org/10.1109/la-cci48322.2021.9769794openalex-snapshot
A Survey on Security Concerns and Their Actual Solutions for using FPGAs in Cloud Computing
inferred← citeshttps://doi.org/10.1109/seed61283.2024.00025openalex-snapshot
Aggregate Encryption Individual Decryption for FPGA Bitstream Protection on Cloud
inferred← citeshttps://doi.org/10.1109/tcc.2026.3698470openalex-snapshot
Toward FPGA Cloud Security: A Ring Oscillator-Free and Low-Power Attack Circuit
inferred← citeshttps://doi.org/10.1109/tdsc.2023.3324935openalex-snapshot
A Secure Computing System With Hardware-Efficient Lazy Bonsai Merkle Tree for FPGA-Attached Embedded Memory
inferred← citeshttps://doi.org/10.1109/trustcom60117.2023.00358openalex-snapshot
Dynamic Scheduling of AES Cores for Aperiodic Tasks on Multi-tenant Cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3498337openalex-snapshot
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era
inferred← citeshttps://doi.org/10.1145/3506713openalex-snapshot
The Future of FPGA Acceleration in Datacenters and the Cloud
inferred← citeshttps://doi.org/10.1145/3544102openalex-snapshot
Microarchitectural Attacks in Heterogeneous Systems: A Survey
inferred← citeshttps://doi.org/10.1145/3561515openalex-snapshot
A Survey on FPGA Cybersecurity Design Strategies
inferred← citeshttps://doi.org/10.1145/3595179openalex-snapshot
HMT: A Hardware-centric Hybrid Bonsai Merkle Tree Algorithm for High-performance Authentication
inferred← citeshttps://doi.org/10.1145/3713078openalex-snapshot
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy
inferred← citeshttps://doi.org/10.1145/3731545.3731582openalex-snapshot
F3: An FPGA-accelerated FaaS Framework
inferred← citeshttps://doi.org/10.1145/3769295openalex-snapshot
GreyConE+: Efficient Rare-Target Test Generation for FPGA HLS Designs
inferred← citeshttps://doi.org/10.3233/jifs-235130openalex-snapshot
RETRACTED: Service application model design for users using fuzzy semantic ontology model in cloud computing
inferred← citeshttps://doi.org/10.32628/ijsrset25122169openalex-snapshot
AI-Driven Cloud Services for Guaranteed Disaster Recovery, Improved Fault Tolerance, and Transparent High Availability in Dynamic Cloud Systems
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