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Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Applications of machine learning techniques in side-channel attacks: a survey
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Power Analysis Attack of an AES GPU Implementation
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Fault Attacks on Secure Embedded Software: Threats, Design, and Evaluation
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A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA
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2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)
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Electromagnetic Analysis Attack on an FPGA Implementation of an Elliptic Curve Cryptosystem
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Clock Glitch Attacks in the Presence of Heating
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2012 Workshop on Fault Diagnosis and Tolerance in Cryptography
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Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey
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Power Wasting Circuits for Cloud FPGA Attacks
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rCUDA: Reducing the number of GPU-based accelerators in high performance clusters
inferredcites →https://doi.org/10.1109/hst.2009.5225057openalex-snapshot
Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs
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inferredcites →https://doi.org/10.1109/iccd.2015.7357115openalex-snapshot
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inferredcites →https://doi.org/10.1109/iccitechnol.2012.6285774openalex-snapshot
Implementation of CPA analysis against AES design on FPGA
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HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires
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Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs
inferredcites →https://doi.org/10.1109/icfpt51103.2020.00050openalex-snapshot
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs
inferredcites →https://doi.org/10.1109/icpp.2013.98openalex-snapshot
Effects of Dynamic Voltage and Frequency Scaling on a K20 GPU
inferredcites →https://doi.org/10.1109/isca45697.2020.00059openalex-snapshot
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
inferredcites →https://doi.org/10.1109/ises50453.2020.00041openalex-snapshot
Tandem Deep Learning Side-Channel Attack Against FPGA Implementation of AES
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2020 21st International Symposium on Quality Electronic Design (ISQED)
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26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection
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IEEE European Test Symposium (ETS)
inferredcites →https://doi.org/10.1109/jproc.2005.862424openalex-snapshot
The Sorcerer's Apprentice Guide to Fault Attacks
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Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures
inferredcites →https://doi.org/10.1109/lca.2016.2614497openalex-snapshot
Counter-Based Tree Structure for Row Hammering Mitigation in DRAM
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Side-Channel-Based Code-Execution Monitoring Systems: A Survey
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inferredcites →https://doi.org/10.1109/reconfig48160.2019.8994789openalex-snapshot
High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs
inferredcites →https://doi.org/10.1109/sp36276.2017openalex-snapshot
2017 IEEE Symposium on Security and Privacy (SP)
inferredcites →https://doi.org/10.1109/sp37863.2019openalex-snapshot
2019 IEEE Symposium on Security and Privacy (SP)
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2020 IEEE Symposium on Security and Privacy (SP)
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Automatic Application of Power Analysis Countermeasures
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Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization
inferredcites →https://doi.org/10.1109/tc.2020.3013196openalex-snapshot
SCAUL: Power Side-Channel Analysis With Unsupervised Learning
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Instruction Sequence Identification and Disassembly Using Power Supply Side-Channel Analysis
inferredcites →https://doi.org/10.1109/tifs.2017.2762826openalex-snapshot
Capacity of the EM Covert/Side-Channel Created by the Execution of Instructions in a Processor
inferredcites →https://doi.org/10.1109/tifs.2020.3023278openalex-snapshot
Side-Channel Attacks With Multi-Thread Mixed Leakage
inferredcites →https://doi.org/10.1109/tifs.2020.3046858openalex-snapshot
Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint
inferredcites →https://doi.org/10.1109/trustcom/bigdatase.2018.00145openalex-snapshot
Website Fingerprinting by Power Estimation Based Side-Channel Attacks on Android 7
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Hardware Designer's Guide to Fault Attacks
inferredcites →https://doi.org/10.1109/tvlsi.2019.2919644openalex-snapshot
The Costs of Confidentiality in Virtualized FPGAs
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Countermeasures against fault attacks on software implemented AES
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Making DRAM Stronger Against Row Hammering
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Remote inter-chip power analysis side-channel attacks at board-level
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In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms
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Information leakage from FPGA routing and logic elements
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On-Device Power Analysis Across Hardware Security Domains.
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A Comprehensive Study of Deep Learning for Side-Channel Analysis
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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