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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/5.726791openalex-snapshot
Gradient-based learning applied to document recognition
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/fccm.2017.25openalex-snapshot
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
inferredcites →https://doi.org/10.1109/hpca.2015.7056066openalex-snapshot
SNNAP: Approximate computing on programmable SoCs via neural acceleration
inferredcites →https://doi.org/10.1109/hpca.2017.29openalex-snapshot
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/hpca.2018.00042openalex-snapshot
G-TSC: Timestamp Based Coherence for GPUs
inferredcites →https://doi.org/10.1109/hpca.2019.00029openalex-snapshot
Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/iccad.2015.7372595openalex-snapshot
PARADE: A cycle-accurate full-system simulation Platform for Accelerator-Rich Architectural Design and Exploration
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942048openalex-snapshot
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942127openalex-snapshot
MAGNet: A Modular Accelerator Generator for Neural Networks
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942149openalex-snapshot
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
inferredcites →https://doi.org/10.1109/icpr.2000.905263openalex-snapshot
Proceedings 15th International Conference on Pattern Recognition. ICPR-2000
inferredcites →https://doi.org/10.1109/isca.2018.00051openalex-snapshot
EVA²: Exploiting Temporal Redundancy in Live Computer Vision
inferredcites →https://doi.org/10.1109/isca.2018.00052openalex-snapshot
Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision
inferredcites →https://doi.org/10.1109/ispass.2019.00042openalex-snapshot
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
inferredcites →https://doi.org/10.1109/ispass48437.2020.00016openalex-snapshot
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
inferredcites →https://doi.org/10.1109/isscc.2016.7418007openalex-snapshot
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
inferredcites →https://doi.org/10.1109/lca.2020.2979965openalex-snapshot
Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference
inferredcites →https://doi.org/10.1109/micro.2016.7783722openalex-snapshot
Stripes: Bit-serial deep neural network computing
inferredcites →https://doi.org/10.1109/micro.2016.7783725openalex-snapshot
Fused-layer CNN accelerators
inferredcites →https://doi.org/10.1109/micro.2016.7783751openalex-snapshot
Co-designing accelerators and SoC interfaces using gem5-Aladdin
inferredcites →https://doi.org/10.1109/tcad.2016.2587683openalex-snapshot
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
inferredcites →https://doi.org/10.1109/tvlsi.2014.2334635openalex-snapshot
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models
inferredcites →https://doi.org/10.1145/2513683.2513688openalex-snapshot
Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3173162.3173177openalex-snapshot
Google Workloads for Consumer Devices
inferredcites →https://doi.org/10.1145/3316781.3317875openalex-snapshot
Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management
inferredcites →https://doi.org/10.1145/3352460.3358252openalex-snapshot
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow
inferredcites →https://doi.org/10.23919/fpl.2017.8056775openalex-snapshot
PAAS: A system level simulator for heterogeneous computing architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-42478-6_27openalex-snapshot
Approximate Communication in Network-on-Chips for Training and Inference of Image Classification Models
inferred← citeshttps://doi.org/10.1016/j.comnet.2023.109759openalex-snapshot
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems
inferred← citeshttps://doi.org/10.1109/access.2021.3118094openalex-snapshot
Optimization of Communication Schemes for DMA-Controlled Accelerators
inferred← citeshttps://doi.org/10.1109/access.2021.3119516openalex-snapshot
System-Level Communication Performance Estimation for DMA-Controlled Accelerators
inferred← citeshttps://doi.org/10.1109/aicconf64766.2025.11064289openalex-snapshot
Integrating Cognitive Models into Network-on-Chip Architectures for Resilient and Adaptive Autonomous Systems
inferred← citeshttps://doi.org/10.1109/asap57973.2023.00042openalex-snapshot
SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators
inferred← citeshttps://doi.org/10.1109/asicon52560.2021.9620327openalex-snapshot
Optimization of Node-clustering-based DAG partition targeting NVDLA Architecture
inferred← citeshttps://doi.org/10.1109/asid52932.2021.9651675openalex-snapshot
Simulators for Deep Neural Network Accelerator Design and Analysis: A Brief Review
inferred← citeshttps://doi.org/10.1109/dsd57027.2022.00054openalex-snapshot
Hardware-Software Codesign of a CNN Accelerator
inferred← citeshttps://doi.org/10.1109/icecet63943.2025.11472144openalex-snapshot
HW-aware Neural Architecture Search Using Genetic Optimisation: In-Memory Compute vs NPU
inferred← citeshttps://doi.org/10.1109/iiswc53511.2021.00028openalex-snapshot
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators
inferred← citeshttps://doi.org/10.1109/iiswc59245.2023.00014openalex-snapshot
MMBench: Benchmarking End-to-End Multi-modal DNNs and Understanding Their Hardware-Software Implications
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00073openalex-snapshot
A Comparative Study on Simulation Frameworks for AI Accelerator Evaluation
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937422openalex-snapshot
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models
inferred← citeshttps://doi.org/10.1109/ispass48437.2020.00016openalex-snapshot
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00042openalex-snapshot
Architecture-Level Energy Estimation for Heterogeneous Computing Systems
inferred← citeshttps://doi.org/10.1109/ispass55109.2022.00042openalex-snapshot
Bifrost: End-to-End Evaluation and optimization of Reconfigurable DNN Accelerators
inferred← citeshttps://doi.org/10.1109/isscc42614.2022.9731757openalex-snapshot
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance
inferred← citeshttps://doi.org/10.1109/jiot.2022.3209401openalex-snapshot
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators
inferred← citeshttps://doi.org/10.1109/jssc.2021.3115466openalex-snapshot
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators
inferred← citeshttps://doi.org/10.1109/jssc.2022.3214170openalex-snapshot
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance
inferred← citeshttps://doi.org/10.1109/lca.2021.3097253openalex-snapshot
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators
inferred← citeshttps://doi.org/10.1109/lca.2024.3484648openalex-snapshot
ONNXim: A Fast, Cycle-Level Multi-Core NPU Simulator
inferred← citeshttps://doi.org/10.1109/lca.2026.3667792openalex-snapshot
EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations
inferred← citeshttps://doi.org/10.1109/mascots64422.2024.10786578openalex-snapshot
Fast and Accurate DNN Performance Estimation across Diverse Hardware Platforms
inferred← citeshttps://doi.org/10.1109/mcas.2024.3359571openalex-snapshot
Chiplet-GAN: Chiplet-Based Accelerator Design for Scalable Generative Adversarial Network Inference [Feature]
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00091openalex-snapshot
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance
inferred← citeshttps://doi.org/10.1109/nas55553.2022.9925540openalex-snapshot
Approximate Network-on-Chips with Application to Image Classification
inferred← citeshttps://doi.org/10.1109/sbac-pad53543.2021.00015openalex-snapshot
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference
inferred← citeshttps://doi.org/10.1109/socc52499.2021.9739212openalex-snapshot
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips
inferred← citeshttps://doi.org/10.1109/tc.2021.3059962openalex-snapshot
ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators
inferred← citeshttps://doi.org/10.1109/tcad.2022.3232070openalex-snapshot
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices
inferred← citeshttps://doi.org/10.1109/tcad.2023.3333290openalex-snapshot
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3430831openalex-snapshot
A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training
inferred← citeshttps://doi.org/10.1109/tetc.2022.3162165openalex-snapshot
A Technique for Approximate Communication in Network-on-Chips for Image Classification
inferred← citeshttps://doi.org/10.1145/3466752.3480095openalex-snapshot
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference
inferred← citeshttps://doi.org/10.1145/3503222.3507754openalex-snapshot
GPUReplay: a 50-KB GPU stack for client ML
inferred← citeshttps://doi.org/10.1145/3531437.3539711openalex-snapshot
A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
inferred← citeshttps://doi.org/10.1145/3604802openalex-snapshot
A Survey of Design and Optimization for Systolic Array-based DNN Accelerators
inferred← citeshttps://doi.org/10.1145/3613424.3614277openalex-snapshot
Path Forward Beyond Simulators: Fast and Accurate GPU Execution Time Prediction for DNN Workloads
inferred← citeshttps://doi.org/10.1145/3625223.3649265openalex-snapshot
Fast and Accurate Virtual Prototyping of an NPU with Analytical Memory Modeling
inferred← citeshttps://doi.org/10.1145/3650200.3656592openalex-snapshot
LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators
inferred← citeshttps://doi.org/10.1145/3661997openalex-snapshot
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips
inferred← citeshttps://doi.org/10.1145/3670404openalex-snapshot
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework
inferred← citeshttps://doi.org/10.1145/3706598.3713249openalex-snapshot
Advancing HCI with Neuromorphic Technology: Guidelines for Designing User-Friendly Developer Tools for Neuromorphic Development
inferred← citeshttps://doi.org/10.1145/3711821openalex-snapshot
HopScotch: A Holistic Approach to Data Layout-Aware Mapping on NPUs for High-Performance DNN Inference
inferred← citeshttps://doi.org/10.1145/3716368.3735158openalex-snapshot
Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
inferred← citeshttps://doi.org/10.1145/3716368.3735197openalex-snapshot
Fast, Transparent and Accurate Simulation of Thousand Processing-in-Memory Cores
inferred← citeshttps://doi.org/10.1145/3725843.3756045openalex-snapshot
PyTorchSim: A Comprehensive, Fast, and Accurate NPU Simulation Framework
inferred← citeshttps://doi.org/10.1145/3729169openalex-snapshot
NoCDAS: A Cycle-Accurate NoC-Based Deep Neural Network Accelerator Simulator
inferred← citeshttps://doi.org/10.1145/3757742openalex-snapshot
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators
inferred← citeshttps://doi.org/10.1145/3803551openalex-snapshot
Mitigating the Bandwidth Wall via Data-Streaming System–Accelerator Co-Design
inferred← citeshttps://doi.org/10.1145/3820047openalex-snapshot
FaStrA: Fast and Efficient Network Structure-Aware Layer Fusion on Deep Learning Accelerators
inferred← citeshttps://doi.org/10.2514/1.i010916openalex-snapshot
On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors
inferred← citeshttps://doi.org/10.32604/csse.2022.022319openalex-snapshot
The Double Edge Sword Based Distributed Executor Service
inferred← citeshttps://doi.org/10.3390/electronics13244971openalex-snapshot
Fast Design Space Exploration for Always-On Neural Networks
inferred← citeshttps://doi.org/10.34133/icomputing.0040openalex-snapshot
Compiler Technologies in Deep Learning Co-Design: A Survey
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