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Compiler Technologies in Deep Learning Co-Design: A Survey
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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The Verilog® Hardware Description Language
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Implementation of deep neural networks on FPGA-CPU platform using Xilinx SDSOC
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Deep Learning: A Comprehensive Overview on Techniques, Taxonomy, Applications and Research Directions
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A Survey of Accelerator Architectures for Deep Neural Networks
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A survey of techniques for optimizing deep learning on GPUs
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A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives
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System-Level Synthesis Using Evolutionary Algorithms
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Learning representations by back-propagating errors
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Neural networks and physical systems with emergent collective computational abilities.
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An analog neural network processor with programmable topology
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Hardware-software cosynthesis for digital systems
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Hardware-software cosynthesis for microcontrollers
inferredcites →https://doi.org/10.1109/cgo51591.2021.9370308openalex-snapshot
MLIR: Scaling Compiler Infrastructure for Domain Specific Computation
inferredcites →https://doi.org/10.1109/cvpr.2018.00286openalex-snapshot
Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference
inferredcites →https://doi.org/10.1109/cvpr.2018.00716openalex-snapshot
ShuffleNet: An Extremely Efficient Convolutional Neural Network for Mobile Devices
inferredcites →https://doi.org/10.1109/cvpr.2018.00821openalex-snapshot
CLIP-Q: Deep Network Compression Learning by In-parallel Pruning-Quantization
inferredcites →https://doi.org/10.1109/dac18074.2021.9586216openalex-snapshot
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration
inferredcites →https://doi.org/10.1109/hpca.2019.00027openalex-snapshot
HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array
inferredcites →https://doi.org/10.1109/hpca47549.2020.00036openalex-snapshot
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators
inferredcites →https://doi.org/10.1109/hpca53966.2022.00060openalex-snapshot
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
inferredcites →https://doi.org/10.1109/hpec55821.2022.9926331openalex-snapshot
AI and ML Accelerator Survey and Trends
inferredcites →https://doi.org/10.1109/iccad.2017.8203780openalex-snapshot
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942127openalex-snapshot
MAGNet: A Modular Accelerator Generator for Neural Networks
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942149openalex-snapshot
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
inferredcites →https://doi.org/10.1109/icess.2019.8782480openalex-snapshot
An In-depth Comparison of Compilers for Deep Neural Networks on Hardware
inferredcites →https://doi.org/10.1109/ipdpsw.2018.00091openalex-snapshot
NVIDIA Tensor Core Programmability, Performance & Precision
inferredcites →https://doi.org/10.1109/ispass.2019.00042openalex-snapshot
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
inferredcites →https://doi.org/10.1109/isscc.2019.8662396openalex-snapshot
1.1 Deep Learning Hardware: Past, Present, and Future
inferredcites →https://doi.org/10.1109/jproc.2011.2182009openalex-snapshot
Hardware/Software Codesign: The Past, the Present, and Predicting the Future
inferredcites →https://doi.org/10.1109/jproc.2020.2976475openalex-snapshot
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey
inferredcites →https://doi.org/10.1109/llvmhpc54804.2021.00009openalex-snapshot
A High Performance Sparse Tensor Algebra Compiler in MLIR
inferredcites →https://doi.org/10.1109/mc.2008.209openalex-snapshot
Amdahl's Law in the Multicore Era
inferredcites →https://doi.org/10.1109/mm.2017.54openalex-snapshot
Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators
inferredcites →https://doi.org/10.1109/msp.2017.2738401openalex-snapshot
Deep Multimodal Learning: A Survey on Recent Advances and Trends
inferredcites →https://doi.org/10.1109/ojcas.2021.3083332openalex-snapshot
FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons
inferredcites →https://doi.org/10.1109/sc.2018.00069openalex-snapshot
Anatomy of High-Performance Deep Learning Convolutions on SIMD Architectures
inferredcites →https://doi.org/10.1109/socc.2006.283880openalex-snapshot
Platform-Based Behavior-Level and System-Level Synthesis
inferredcites →https://doi.org/10.1109/tpds.2020.3030548openalex-snapshot
The Deep Learning Compiler: A Comprehensive Survey
inferredcites →https://doi.org/10.1126/science.1127647openalex-snapshot
Reducing the Dimensionality of Data with Neural Networks
inferredcites →https://doi.org/10.1126/science.220.4598.671openalex-snapshot
Optimization by Simulated Annealing
inferredcites →https://doi.org/10.1145/1146909.1147025openalex-snapshot
An efficient and versatile scheduling algorithm based on SDC formulation
inferredcites →https://doi.org/10.1145/2544375.2544392openalex-snapshot
Energy-aware task mapping and scheduling for reliable embedded computing systems
inferredcites →https://doi.org/10.1145/3065386openalex-snapshot
ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3192366.3192379openalex-snapshot
Spatial: a language and compiler for application accelerators
inferredcites →https://doi.org/10.1145/3211346.3211348openalex-snapshot
Relay: a new IR for machine learning frameworks
inferredcites →https://doi.org/10.1145/3240765.3243479openalex-snapshot
Hardware-aware machine learning
inferredcites →https://doi.org/10.1145/3282307openalex-snapshot
A new golden age for computer architecture
inferredcites →https://doi.org/10.1145/3306346.3322967openalex-snapshot
Learning to optimize halide with tree search and random programs
inferredcites →https://doi.org/10.1145/3315508.3329973openalex-snapshot
Triton: an intermediate language and compiler for tiled neural network computations
inferredcites →https://doi.org/10.1145/3316781.3326334openalex-snapshot
Toward an Open-Source Digital Flow
inferredcites →https://doi.org/10.1145/3352460.3358252openalex-snapshot
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow
inferredcites →https://doi.org/10.1145/3361682openalex-snapshot
Domain-specific hardware accelerators
inferredcites →https://doi.org/10.1145/3373087.3375887openalex-snapshot
Xilinx Vitis Unified Software Platform
inferredcites →https://doi.org/10.1145/3373376.3378534openalex-snapshot
PatDNN: Achieving Real-Time DNN Execution on Mobile Devices with Pattern-based Weight Pruning
inferredcites →https://doi.org/10.1145/3385412.3385974openalex-snapshot
Predictable accelerator design with time-sensitive affine types
inferredcites →https://doi.org/10.1145/3445814.3446712openalex-snapshot
A compiler infrastructure for accelerator generators
inferredcites →https://doi.org/10.1145/3453483.3454106openalex-snapshot
AKG: automatic kernel generation for neural processing units using polyhedral transformations
inferredcites →https://doi.org/10.1145/3478684.3479261openalex-snapshot
Automated HW/SW co-design for edge AI
inferredcites →https://doi.org/10.1145/3494534openalex-snapshot
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
inferredcites →https://doi.org/10.1145/3519939.3523700openalex-snapshot
IRDL: an IR definition language for SSA compilers
inferredcites →https://doi.org/10.1145/3533251openalex-snapshot
A Framework for Neural Network Architecture and Compile Co-optimization
inferredcites →https://doi.org/10.1145/3544559openalex-snapshot
Compiler Support for Sparse Tensor Computations in MLIR
inferredcites →https://doi.org/10.1561/2000000039openalex-snapshot
Deep Learning: Methods and Applications
inferredcites →https://doi.org/10.1609/aaai.v34i04.5954openalex-snapshot
PCONV: The Missing but Desirable Sparsity in DNN Weight Pruning for Real-Time Execution on Mobile Devices
inferredcites →https://doi.org/10.21437/interspeech.2010-343openalex-snapshot
Recurrent neural network based language model
inferredcites →https://doi.org/10.23919/date48585.2020.9116474openalex-snapshot
You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design
inferredcites →https://doi.org/10.4230/lipics.ecoop.2020.15openalex-snapshot
Static Analysis of Shape in TensorFlow Programs
inferredcites →https://doi.org/10.4230/lipics.ecrts.2024.13openalex-snapshot
DeepTrust^RT: Confidential Deep Neural Inference Meets Real-Time!
inferredcites →https://doi.org/10.48550/arxiv.1404.5997openalex-snapshot
One weird trick for parallelizing convolutional neural networks
inferredcites →https://doi.org/10.48550/arxiv.1512.01274openalex-snapshot
MXNet: A Flexible and Efficient Machine Learning Library for Heterogeneous Distributed Systems
inferredcites →https://doi.org/10.48550/arxiv.1602.07360openalex-snapshot
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size
inferredcites →https://doi.org/10.48550/arxiv.1611.01578openalex-snapshot
Neural Architecture Search with Reinforcement Learning
inferredcites →https://doi.org/10.48550/arxiv.1801.08058openalex-snapshot
Intel nGraph: An Intermediate Representation, Compiler, and Executor for Deep Learning
inferredcites →https://doi.org/10.48550/arxiv.1802.04730openalex-snapshot
Tensor Comprehensions: Framework-Agnostic High-Performance Machine Learning Abstractions
inferredcites →https://doi.org/10.48550/arxiv.1803.05900openalex-snapshot
Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
inferredcites →https://doi.org/10.48550/arxiv.1805.00907openalex-snapshot
Glow: Graph Lowering Compiler Techniques for Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.1805.08166openalex-snapshot
Learning to Optimize Tensor Programs
inferredcites →https://doi.org/10.48550/arxiv.1808.05377openalex-snapshot
Neural Architecture Search: A Survey
inferredcites →https://doi.org/10.48550/arxiv.1912.01703openalex-snapshot
PyTorch: An Imperative Style, High-Performance Deep Learning Library
inferredcites →https://doi.org/10.48550/arxiv.1912.10207openalex-snapshot
Towards Efficient Training for Neural Network Quantization
inferredcites →https://doi.org/10.48550/arxiv.2003.00532openalex-snapshot
High Performance Code Generation in MLIR: An Early Case Study with GEMM
inferredcites →https://doi.org/10.48550/arxiv.2003.02838openalex-snapshot
Accelerator-aware Neural Network Design using AutoML
inferredcites →https://doi.org/10.48550/arxiv.2006.06762openalex-snapshot
Ansor: Generating High-Performance Tensor Programs for Deep Learning
inferredcites →https://doi.org/10.48550/arxiv.2007.10319openalex-snapshot
MCUNet: Tiny Deep Learning on IoT Devices
inferredcites →https://doi.org/10.48550/arxiv.2108.13191openalex-snapshot
High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results
inferredcites →https://doi.org/10.48550/arxiv.2210.15016openalex-snapshot
TPU-MLIR: A Compiler For TPU Using MLIR
inferredcites →https://doi.org/10.7551/mitpress/3927.001.0001openalex-snapshot
An Introduction to Genetic Algorithms
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.70164openalex-snapshot
Fusing the Polyhedral and Tensor Compilers to Accelerate Scientific Computing Kernels
inferred← citeshttps://doi.org/10.1007/978-3-031-96239-4_28openalex-snapshot
Optimizing Cache Utilization in CPU Compilation Through Compiler Autotuning
inferred← citeshttps://doi.org/10.1007/978-3-031-98208-8_13openalex-snapshot
COMPASS: An Agent for MLIR Compilation Pass Pipeline Generation
inferred← citeshttps://doi.org/10.1007/978-981-96-2830-8_14openalex-snapshot
VConv: Autotiling Convolution Algorithm Based on MLIR for Multi-core Vector accelerators
inferred← citeshttps://doi.org/10.1016/b978-0-443-45574-2.00008-3openalex-snapshot
Advanced computing: the journey toward post-exascale era
inferred← citeshttps://doi.org/10.1016/j.cpc.2024.109187openalex-snapshot
XLB: A differentiable massively parallel lattice Boltzmann library in Python
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A Software–Hardware Co-optimization and Evaluation Framework for Modular End-to-End Autonomous Driving
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Pose estimation of bolster spring based on projection roundness and genetic algorithm in narrow space
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103895openalex-snapshot
Graph-based clustering cost model for performance optimization in deep learning compilers
inferred← citeshttps://doi.org/10.1088/1742-6596/2898/1/012004openalex-snapshot
Analysis of optimal planting scheme based on the North China region
inferred← citeshttps://doi.org/10.1109/aetcse69203.2026.11503963openalex-snapshot
Shared Memory Optimization of the Triton Compiler for Domestic NPU
inferred← citeshttps://doi.org/10.1109/cac67268.2025.11486656openalex-snapshot
A Hybrid Deep Learning and Genetic Algorithm Approach for Adaptive Educational Platforms
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Design and Application of Objective Questions Generating Examination Paper System Based on Random Extraction Algorithm
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VCNN: A compiler of CNNs based on MLIR for multi-core vector accelerators
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Exploring the Feasibility of End-to-End Large Language Model as a Compiler
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EARTH: Efficient Architecture for RISC-V Vector Memory Access
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Deployment-Aware Compression of Large Language Models for Edge Intelligence: A System-Level Survey
inferred← citeshttps://doi.org/10.1145/3650212.3680360openalex-snapshot
Fuzzing MLIR Compiler Infrastructure via Operation Dependency Analysis
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Mosaic: Exploiting Instruction-Level Parallelism on Deep Learning Accelerators with iTex Tessellation
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Titan-I: An Open-Source, High Performance RISC-V Vector Core
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Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support
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Using Task Graph Caching to Accelerate TVM Code Generation
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